Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=64883ab0e3386d72112a9091d886352a7b4b8bf6
Commit:     64883ab0e3386d72112a9091d886352a7b4b8bf6
Parent:     d291cf83639a0e0b67ff783b6ed29c0a747d4901
Author:     Thomas Gleixner <[EMAIL PROTECTED]>
AuthorDate: Wed Jan 30 13:30:35 2008 +0100
Committer:  Ingo Molnar <[EMAIL PROTECTED]>
CommitDate: Wed Jan 30 13:30:35 2008 +0100

    x86: cleanup mpspec variants
    
    Bring the mpspec variants into sync to prepare merging and
    paravirt support.
    
    Signed-off-by: Thomas Gleixner <[EMAIL PROTECTED]>
    Signed-off-by: Ingo Molnar <[EMAIL PROTECTED]>
    Signed-off-by: Thomas Gleixner <[EMAIL PROTECTED]>
---
 arch/x86/kernel/mpparse_32.c             |   18 +-
 arch/x86/mach-visws/mpparse.c            |   16 +-
 include/asm-x86/mach-bigsmp/mach_apic.h  |   12 +-
 include/asm-x86/mach-default/mach_apic.h |   18 +-
 include/asm-x86/mach-es7000/mach_apic.h  |   10 +-
 include/asm-x86/mach-numaq/mach_apic.h   |   10 +-
 include/asm-x86/mach-summit/mach_apic.h  |   18 +-
 include/asm-x86/mpspec_32.h              |   49 +++---
 include/asm-x86/mpspec_64.h              |  312 ++++++++----------------------
 include/asm-x86/mpspec_def.h             |   87 +++++----
 10 files changed, 206 insertions(+), 344 deletions(-)

diff --git a/arch/x86/kernel/mpparse_32.c b/arch/x86/kernel/mpparse_32.c
index 7a05a7f..22fc8d7 100644
--- a/arch/x86/kernel/mpparse_32.c
+++ b/arch/x86/kernel/mpparse_32.c
@@ -258,7 +258,7 @@ static void __init MP_ioapic_info (struct mpc_config_ioapic 
*m)
        if (!(m->mpc_flags & MPC_APIC_USABLE))
                return;
 
-       printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
+       printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
                m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
        if (nr_ioapics >= MAX_IO_APICS) {
                printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found 
%d).\n",
@@ -405,9 +405,9 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
 
        mps_oem_check(mpc, oem, str);
 
-       printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
+       printk("APIC at: 0x%X\n", mpc->mpc_lapic);
 
-       /* 
+       /*
         * Save the local APIC address (it might be non-default) -- but only
         * if we're not using ACPI.
         */
@@ -918,14 +918,14 @@ void __init mp_register_ioapic(u8 id, u32 address, u32 
gsi_base)
         */
        mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
        mp_ioapic_routing[idx].gsi_base = gsi_base;
-       mp_ioapic_routing[idx].gsi_end = gsi_base + 
+       mp_ioapic_routing[idx].gsi_end = gsi_base +
                io_apic_get_redir_entries(idx);
 
-       printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
-               "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 
-               mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
-               mp_ioapic_routing[idx].gsi_base,
-               mp_ioapic_routing[idx].gsi_end);
+       printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
+              "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
+              mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
+              mp_ioapic_routing[idx].gsi_base,
+              mp_ioapic_routing[idx].gsi_end);
 }
 
 void __init
diff --git a/arch/x86/mach-visws/mpparse.c b/arch/x86/mach-visws/mpparse.c
index f3c74fa..2a8456a 100644
--- a/arch/x86/mach-visws/mpparse.c
+++ b/arch/x86/mach-visws/mpparse.c
@@ -36,19 +36,19 @@ unsigned int __initdata maxcpus = NR_CPUS;
 
 static void __init MP_processor_info (struct mpc_config_processor *m)
 {
-       int ver, logical_apicid;
+       int ver, logical_apicid;
        physid_mask_t apic_cpus;
-       
+
        if (!(m->mpc_cpuflag & CPU_ENABLED))
                return;
 
        logical_apicid = m->mpc_apicid;
-       printk(KERN_INFO "%sCPU #%d %ld:%ld APIC version %d\n",
-               m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
-               m->mpc_apicid,
-               (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-               (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-               m->mpc_apicver);
+       printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
+              m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
+              m->mpc_apicid,
+              (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+              (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+              m->mpc_apicver);
 
        if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
                boot_cpu_physical_apicid = m->mpc_apicid;
diff --git a/include/asm-x86/mach-bigsmp/mach_apic.h 
b/include/asm-x86/mach-bigsmp/mach_apic.h
index ebd319f..6df235e 100644
--- a/include/asm-x86/mach-bigsmp/mach_apic.h
+++ b/include/asm-x86/mach-bigsmp/mach_apic.h
@@ -110,13 +110,13 @@ static inline int cpu_to_logical_apicid(int cpu)
 }
 
 static inline int mpc_apic_id(struct mpc_config_processor *m,
-                       struct mpc_config_translation *translation_record)
+                             struct mpc_config_translation *translation_record)
 {
-       printk("Processor #%d %ld:%ld APIC version %d\n",
-               m->mpc_apicid,
-               (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-               (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-               m->mpc_apicver);
+       printk("Processor #%d %u:%u APIC version %d\n",
+              m->mpc_apicid,
+              (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+              (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+              m->mpc_apicver);
        return m->mpc_apicid;
 }
 
diff --git a/include/asm-x86/mach-default/mach_apic.h 
b/include/asm-x86/mach-default/mach_apic.h
index 6db1c3b..e3c2c10 100644
--- a/include/asm-x86/mach-default/mach_apic.h
+++ b/include/asm-x86/mach-default/mach_apic.h
@@ -89,15 +89,15 @@ static inline physid_mask_t apicid_to_cpu_present(int 
phys_apicid)
        return physid_mask_of_physid(phys_apicid);
 }
 
-static inline int mpc_apic_id(struct mpc_config_processor *m, 
-                       struct mpc_config_translation *translation_record)
-{
-       printk("Processor #%d %ld:%ld APIC version %d\n",
-                       m->mpc_apicid,
-                       (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-                       (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-                       m->mpc_apicver);
-       return (m->mpc_apicid);
+static inline int mpc_apic_id(struct mpc_config_processor *m,
+                             struct mpc_config_translation *translation_record)
+{
+       printk("Processor #%d %u:%u APIC version %d\n",
+              m->mpc_apicid,
+              (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+              (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+              m->mpc_apicver);
+       return m->mpc_apicid;
 }
 
 static inline void setup_portio_remap(void)
diff --git a/include/asm-x86/mach-es7000/mach_apic.h 
b/include/asm-x86/mach-es7000/mach_apic.h
index caec64b..d23011f 100644
--- a/include/asm-x86/mach-es7000/mach_apic.h
+++ b/include/asm-x86/mach-es7000/mach_apic.h
@@ -131,11 +131,11 @@ static inline int cpu_to_logical_apicid(int cpu)
 
 static inline int mpc_apic_id(struct mpc_config_processor *m, struct 
mpc_config_translation *unused)
 {
-       printk("Processor #%d %ld:%ld APIC version %d\n",
-               m->mpc_apicid,
-               (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-               (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-               m->mpc_apicver);
+       printk("Processor #%d %u:%u APIC version %d\n",
+              m->mpc_apicid,
+              (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+              (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+              m->mpc_apicver);
        return (m->mpc_apicid);
 }
 
diff --git a/include/asm-x86/mach-numaq/mach_apic.h 
b/include/asm-x86/mach-numaq/mach_apic.h
index 5e5e7dd..17e183b 100644
--- a/include/asm-x86/mach-numaq/mach_apic.h
+++ b/include/asm-x86/mach-numaq/mach_apic.h
@@ -101,11 +101,11 @@ static inline int mpc_apic_id(struct mpc_config_processor 
*m,
        int quad = translation_record->trans_quad;
        int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid);
 
-       printk("Processor #%d %ld:%ld APIC version %d (quad %d, apic %d)\n",
-                       m->mpc_apicid,
-                       (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-                       (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-                       m->mpc_apicver, quad, logical_apicid);
+       printk("Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
+              m->mpc_apicid,
+              (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+              (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+              m->mpc_apicver, quad, logical_apicid);
        return logical_apicid;
 }
 
diff --git a/include/asm-x86/mach-summit/mach_apic.h 
b/include/asm-x86/mach-summit/mach_apic.h
index 732f776..062c97f 100644
--- a/include/asm-x86/mach-summit/mach_apic.h
+++ b/include/asm-x86/mach-summit/mach_apic.h
@@ -126,15 +126,15 @@ static inline physid_mask_t apicid_to_cpu_present(int 
apicid)
        return physid_mask_of_physid(0);
 }
 
-static inline int mpc_apic_id(struct mpc_config_processor *m, 
-                       struct mpc_config_translation *translation_record)
-{
-       printk("Processor #%d %ld:%ld APIC version %d\n",
-                       m->mpc_apicid,
-                       (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
-                       (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
-                       m->mpc_apicver);
-       return (m->mpc_apicid);
+static inline int mpc_apic_id(struct mpc_config_processor *m,
+                             struct mpc_config_translation *translation_record)
+{
+       printk("Processor #%d %u:%u APIC version %d\n",
+              m->mpc_apicid,
+              (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
+              (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
+              m->mpc_apicver);
+       return m->mpc_apicid;
 }
 
 static inline void setup_portio_remap(void)
diff --git a/include/asm-x86/mpspec_32.h b/include/asm-x86/mpspec_32.h
index f213493..bb73185 100644
--- a/include/asm-x86/mpspec_32.h
+++ b/include/asm-x86/mpspec_32.h
@@ -1,34 +1,37 @@
 #ifndef __ASM_MPSPEC_H
 #define __ASM_MPSPEC_H
 
-#include <linux/cpumask.h>
 #include <asm/mpspec_def.h>
 #include <mach_mpspec.h>
 
-extern int mp_bus_id_to_type [MAX_MP_BUSSES];
-extern int mp_bus_id_to_node [MAX_MP_BUSSES];
-extern int mp_bus_id_to_local [MAX_MP_BUSSES];
-extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
-extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
+extern int mp_bus_id_to_type[MAX_MP_BUSSES];
+extern int mp_bus_id_to_node[MAX_MP_BUSSES];
+extern int mp_bus_id_to_local[MAX_MP_BUSSES];
+extern int quad_local_to_mp_bus_id[NR_CPUS/4][4];
 
 extern unsigned int def_to_bigsmp;
+extern int apic_version[MAX_APICS];
+extern int pic_mode;
+
+extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
+
 extern unsigned int boot_cpu_physical_apicid;
 extern int smp_found_config;
-extern void find_smp_config (void);
-extern void get_smp_config (void);
 extern int nr_ioapics;
-extern int apic_version [MAX_APICS];
 extern int mp_irq_entries;
-extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
+extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 extern int mpc_default_type;
 extern unsigned long mp_lapic_addr;
-extern int pic_mode;
+
+extern void find_smp_config (void);
+extern void get_smp_config (void);
 
 #ifdef CONFIG_ACPI
 extern void mp_register_lapic (u8 id, u8 enabled);
 extern void mp_register_lapic_address (u64 address);
 extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
-extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 
gsi);
+extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger,
+                                   u32 gsi);
 extern void mp_config_acpi_legacy_irqs (void);
 extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
 #endif /* CONFIG_ACPI */
@@ -50,7 +53,7 @@ typedef struct physid_mask physid_mask_t;
 #define physids_and(dst, src1, src2)           bitmap_and((dst).mask, 
(src1).mask, (src2).mask, MAX_APICS)
 #define physids_or(dst, src1, src2)            bitmap_or((dst).mask, 
(src1).mask, (src2).mask, MAX_APICS)
 #define physids_clear(map)                     bitmap_zero((map).mask, 
MAX_APICS)
-#define physids_complement(dst, src)           
bitmap_complement((dst).mask,(src).mask, MAX_APICS)
+#define physids_complement(dst, src)           bitmap_complement((dst).mask, 
(src).mask, MAX_APICS)
 #define physids_empty(map)                     bitmap_empty((map).mask, 
MAX_APICS)
 #define physids_equal(map1, map2)              bitmap_equal((map1).mask, 
(map2).mask, MAX_APICS)
 #define physids_weight(map)                    bitmap_weight((map).mask, 
MAX_APICS)
@@ -58,18 +61,18 @@ typedef struct physid_mask physid_mask_t;
 #define physids_shift_left(d, s, n)            bitmap_shift_left((d).mask, 
(s).mask, n, MAX_APICS)
 #define physids_coerce(map)                    ((map).mask[0])
 
-#define physids_promote(physids)                                               
\
-       ({                                                                      
\
-               physid_mask_t __physid_mask = PHYSID_MASK_NONE;                 
\
-               __physid_mask.mask[0] = physids;                                
\
-               __physid_mask;                                                  
\
+#define physids_promote(physids)                                       \
+       ({                                                              \
+               physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
+               __physid_mask.mask[0] = physids;                        \
+               __physid_mask;                                          \
        })
 
-#define physid_mask_of_physid(physid)                                          
\
-       ({                                                                      
\
-               physid_mask_t __physid_mask = PHYSID_MASK_NONE;                 
\
-               physid_set(physid, __physid_mask);                              
\
-               __physid_mask;                                                  
\
+#define physid_mask_of_physid(physid)                                  \
+       ({                                                              \
+               physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
+               physid_set(physid, __physid_mask);                      \
+               __physid_mask;                                          \
        })
 
 #define PHYSID_MASK_ALL                { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
diff --git a/include/asm-x86/mpspec_64.h b/include/asm-x86/mpspec_64.h
dissimilarity index 66%
index 017fddb..16eab20 100644
--- a/include/asm-x86/mpspec_64.h
+++ b/include/asm-x86/mpspec_64.h
@@ -1,233 +1,79 @@
-#ifndef __ASM_MPSPEC_H
-#define __ASM_MPSPEC_H
-
-/*
- * Structure definitions for SMP machines following the
- * Intel Multiprocessing Specification 1.1 and 1.4.
- */
-
-/*
- * This tag identifies where the SMP configuration
- * information is. 
- */
- 
-#define SMP_MAGIC_IDENT        (('_'<<24)|('P'<<16)|('M'<<8)|'_')
-
-/*
- * A maximum of 255 APICs with the current APIC ID architecture.
- */
-#define MAX_APICS 255
-
-struct intel_mp_floating
-{
-       char mpf_signature[4];          /* "_MP_"                       */
-       unsigned int mpf_physptr;       /* Configuration table address  */
-       unsigned char mpf_length;       /* Our length (paragraphs)      */
-       unsigned char mpf_specification;/* Specification version        */
-       unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
-       unsigned char mpf_feature1;     /* Standard or configuration ?  */
-       unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
-       unsigned char mpf_feature3;     /* Unused (0)                   */
-       unsigned char mpf_feature4;     /* Unused (0)                   */
-       unsigned char mpf_feature5;     /* Unused (0)                   */
-};
-
-struct mp_config_table
-{
-       char mpc_signature[4];
-#define MPC_SIGNATURE "PCMP"
-       unsigned short mpc_length;      /* Size of table */
-       char  mpc_spec;                 /* 0x01 */
-       char  mpc_checksum;
-       char  mpc_oem[8];
-       char  mpc_productid[12];
-       unsigned int mpc_oemptr;        /* 0 if not present */
-       unsigned short mpc_oemsize;     /* 0 if not present */
-       unsigned short mpc_oemcount;
-       unsigned int mpc_lapic; /* APIC address */
-       unsigned int reserved;
-};
-
-/* Followed by entries */
-
-#define        MP_PROCESSOR    0
-#define        MP_BUS          1
-#define        MP_IOAPIC       2
-#define        MP_INTSRC       3
-#define        MP_LINTSRC      4
-
-struct mpc_config_processor
-{
-       unsigned char mpc_type;
-       unsigned char mpc_apicid;       /* Local APIC number */
-       unsigned char mpc_apicver;      /* Its versions */
-       unsigned char mpc_cpuflag;
-#define CPU_ENABLED            1       /* Processor is available */
-#define CPU_BOOTPROCESSOR      2       /* Processor is the BP */
-       unsigned int mpc_cpufeature;            
-#define CPU_STEPPING_MASK 0x0F
-#define CPU_MODEL_MASK 0xF0
-#define CPU_FAMILY_MASK        0xF00
-       unsigned int mpc_featureflag;   /* CPUID feature value */
-       unsigned int mpc_reserved[2];
-};
-
-struct mpc_config_bus
-{
-       unsigned char mpc_type;
-       unsigned char mpc_busid;
-       unsigned char mpc_bustype[6];
-};
-
-/* List of Bus Type string values, Intel MP Spec. */
-#define BUSTYPE_EISA   "EISA"
-#define BUSTYPE_ISA    "ISA"
-#define BUSTYPE_INTERN "INTERN"        /* Internal BUS */
-#define BUSTYPE_MCA    "MCA"
-#define BUSTYPE_VL     "VL"            /* Local bus */
-#define BUSTYPE_PCI    "PCI"
-#define BUSTYPE_PCMCIA "PCMCIA"
-#define BUSTYPE_CBUS   "CBUS"
-#define BUSTYPE_CBUSII "CBUSII"
-#define BUSTYPE_FUTURE "FUTURE"
-#define BUSTYPE_MBI    "MBI"
-#define BUSTYPE_MBII   "MBII"
-#define BUSTYPE_MPI    "MPI"
-#define BUSTYPE_MPSA   "MPSA"
-#define BUSTYPE_NUBUS  "NUBUS"
-#define BUSTYPE_TC     "TC"
-#define BUSTYPE_VME    "VME"
-#define BUSTYPE_XPRESS "XPRESS"
-
-struct mpc_config_ioapic
-{
-       unsigned char mpc_type;
-       unsigned char mpc_apicid;
-       unsigned char mpc_apicver;
-       unsigned char mpc_flags;
-#define MPC_APIC_USABLE                0x01
-       unsigned int mpc_apicaddr;
-};
-
-struct mpc_config_intsrc
-{
-       unsigned char mpc_type;
-       unsigned char mpc_irqtype;
-       unsigned short mpc_irqflag;
-       unsigned char mpc_srcbus;
-       unsigned char mpc_srcbusirq;
-       unsigned char mpc_dstapic;
-       unsigned char mpc_dstirq;
-};
-
-enum mp_irq_source_types {
-       mp_INT = 0,
-       mp_NMI = 1,
-       mp_SMI = 2,
-       mp_ExtINT = 3
-};
-
-#define MP_IRQDIR_DEFAULT      0
-#define MP_IRQDIR_HIGH         1
-#define MP_IRQDIR_LOW          3
-
-
-struct mpc_config_lintsrc
-{
-       unsigned char mpc_type;
-       unsigned char mpc_irqtype;
-       unsigned short mpc_irqflag;
-       unsigned char mpc_srcbusid;
-       unsigned char mpc_srcbusirq;
-       unsigned char mpc_destapic;     
-#define MP_APIC_ALL    0xFF
-       unsigned char mpc_destapiclint;
-};
-
-/*
- *     Default configurations
- *
- *     1       2 CPU ISA 82489DX
- *     2       2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
- *     3       2 CPU EISA 82489DX
- *     4       2 CPU MCA 82489DX
- *     5       2 CPU ISA+PCI
- *     6       2 CPU EISA+PCI
- *     7       2 CPU MCA+PCI
- */
-
-#define MAX_MP_BUSSES 256
-/* Each PCI slot may be a combo card with its own bus.  4 IRQ pins per slot. */
-#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
-extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
-extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
-
-extern unsigned int boot_cpu_physical_apicid;
-extern int smp_found_config;
-extern void find_smp_config (void);
-extern void get_smp_config (void);
-extern int nr_ioapics;
-extern unsigned char apic_version [MAX_APICS];
-extern int mp_irq_entries;
-extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
-extern int mpc_default_type;
-extern unsigned long mp_lapic_addr;
-
-#ifdef CONFIG_ACPI
-extern void mp_register_lapic (u8 id, u8 enabled);
-extern void mp_register_lapic_address (u64 address);
-
-extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
-extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 
gsi);
-extern void mp_config_acpi_legacy_irqs (void);
-extern int mp_register_gsi (u32 gsi, int triggering, int polarity);
-#endif
-
-extern int using_apic_timer;
-
-#define PHYSID_ARRAY_SIZE      BITS_TO_LONGS(MAX_APICS)
-
-struct physid_mask
-{
-       unsigned long mask[PHYSID_ARRAY_SIZE];
-};
-
-typedef struct physid_mask physid_mask_t;
-
-#define physid_set(physid, map)                        set_bit(physid, 
(map).mask)
-#define physid_clear(physid, map)              clear_bit(physid, (map).mask)
-#define physid_isset(physid, map)              test_bit(physid, (map).mask)
-#define physid_test_and_set(physid, map)       test_and_set_bit(physid, 
(map).mask)
-
-#define physids_and(dst, src1, src2)           bitmap_and((dst).mask, 
(src1).mask, (src2).mask, MAX_APICS)
-#define physids_or(dst, src1, src2)            bitmap_or((dst).mask, 
(src1).mask, (src2).mask, MAX_APICS)
-#define physids_clear(map)                     bitmap_zero((map).mask, 
MAX_APICS)
-#define physids_complement(dst, src)           bitmap_complement((dst).mask, 
(src).mask, MAX_APICS)
-#define physids_empty(map)                     bitmap_empty((map).mask, 
MAX_APICS)
-#define physids_equal(map1, map2)              bitmap_equal((map1).mask, 
(map2).mask, MAX_APICS)
-#define physids_weight(map)                    bitmap_weight((map).mask, 
MAX_APICS)
-#define physids_shift_right(d, s, n)           bitmap_shift_right((d).mask, 
(s).mask, n, MAX_APICS)
-#define physids_shift_left(d, s, n)            bitmap_shift_left((d).mask, 
(s).mask, n, MAX_APICS)
-#define physids_coerce(map)                    ((map).mask[0])
-
-#define physids_promote(physids)                                               
\
-       ({                                                                      
\
-               physid_mask_t __physid_mask = PHYSID_MASK_NONE;                 
\
-               __physid_mask.mask[0] = physids;                                
\
-               __physid_mask;                                                  
\
-       })
-
-#define physid_mask_of_physid(physid)                                          
\
-       ({                                                                      
\
-               physid_mask_t __physid_mask = PHYSID_MASK_NONE;                 
\
-               physid_set(physid, __physid_mask);                              
\
-               __physid_mask;                                                  
\
-       })
-
-#define PHYSID_MASK_ALL                { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
-#define PHYSID_MASK_NONE       { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
-
-extern physid_mask_t phys_cpu_present_map;
-
-#endif
-
+#ifndef __ASM_MPSPEC_H
+#define __ASM_MPSPEC_H
+
+#include <asm/mpspec_def.h>
+
+#define MAX_MP_BUSSES 256
+/* Each PCI slot may be a combo card with its own bus.  4 IRQ pins per slot. */
+#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
+extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
+
+extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
+
+extern unsigned int boot_cpu_physical_apicid;
+extern int smp_found_config;
+extern int nr_ioapics;
+extern int mp_irq_entries;
+extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
+extern int mpc_default_type;
+extern unsigned long mp_lapic_addr;
+
+extern void find_smp_config (void);
+extern void get_smp_config (void);
+
+#ifdef CONFIG_ACPI
+extern void mp_register_lapic (u8 id, u8 enabled);
+extern void mp_register_lapic_address (u64 address);
+extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
+extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger,
+                                   u32 gsi);
+extern void mp_config_acpi_legacy_irqs (void);
+extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
+#endif /* CONFIG_ACPI */
+
+#define PHYSID_ARRAY_SIZE      BITS_TO_LONGS(MAX_APICS)
+
+struct physid_mask
+{
+       unsigned long mask[PHYSID_ARRAY_SIZE];
+};
+
+typedef struct physid_mask physid_mask_t;
+
+#define physid_set(physid, map)                        set_bit(physid, 
(map).mask)
+#define physid_clear(physid, map)              clear_bit(physid, (map).mask)
+#define physid_isset(physid, map)              test_bit(physid, (map).mask)
+#define physid_test_and_set(physid, map)       test_and_set_bit(physid, 
(map).mask)
+
+#define physids_and(dst, src1, src2)           bitmap_and((dst).mask, 
(src1).mask, (src2).mask, MAX_APICS)
+#define physids_or(dst, src1, src2)            bitmap_or((dst).mask, 
(src1).mask, (src2).mask, MAX_APICS)
+#define physids_clear(map)                     bitmap_zero((map).mask, 
MAX_APICS)
+#define physids_complement(dst, src)           bitmap_complement((dst).mask, 
(src).mask, MAX_APICS)
+#define physids_empty(map)                     bitmap_empty((map).mask, 
MAX_APICS)
+#define physids_equal(map1, map2)              bitmap_equal((map1).mask, 
(map2).mask, MAX_APICS)
+#define physids_weight(map)                    bitmap_weight((map).mask, 
MAX_APICS)
+#define physids_shift_right(d, s, n)           bitmap_shift_right((d).mask, 
(s).mask, n, MAX_APICS)
+#define physids_shift_left(d, s, n)            bitmap_shift_left((d).mask, 
(s).mask, n, MAX_APICS)
+#define physids_coerce(map)                    ((map).mask[0])
+
+#define physids_promote(physids)                                       \
+       ({                                                              \
+               physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
+               __physid_mask.mask[0] = physids;                        \
+               __physid_mask;                                          \
+       })
+
+#define physid_mask_of_physid(physid)                                  \
+       ({                                                              \
+               physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
+               physid_set(physid, __physid_mask);                      \
+               __physid_mask;                                          \
+       })
+
+#define PHYSID_MASK_ALL                { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
+#define PHYSID_MASK_NONE       { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
+
+extern physid_mask_t phys_cpu_present_map;
+
+#endif
+
diff --git a/include/asm-x86/mpspec_def.h b/include/asm-x86/mpspec_def.h
index 13bafb1..3504617 100644
--- a/include/asm-x86/mpspec_def.h
+++ b/include/asm-x86/mpspec_def.h
@@ -8,52 +8,68 @@
 
 /*
  * This tag identifies where the SMP configuration
- * information is. 
+ * information is.
  */
- 
+
 #define SMP_MAGIC_IDENT        (('_'<<24)|('P'<<16)|('M'<<8)|'_')
 
-#define MAX_MPC_ENTRY 1024
-#define MAX_APICS      256
+#ifdef CONFIG_X86_32
+# define MAX_MPC_ENTRY 1024
+# define MAX_APICS      256
+#else
+/*
+ * A maximum of 255 APICs with the current APIC ID architecture.
+ */
+# define MAX_APICS 255
+#endif
 
 struct intel_mp_floating
 {
-       char mpf_signature[4];          /* "_MP_"                       */
-       unsigned long mpf_physptr;      /* Configuration table address  */
+       char mpf_signature[4];          /* "_MP_"                       */
+       unsigned int mpf_physptr;       /* Configuration table address  */
        unsigned char mpf_length;       /* Our length (paragraphs)      */
        unsigned char mpf_specification;/* Specification version        */
        unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
-       unsigned char mpf_feature1;     /* Standard or configuration ?  */
+       unsigned char mpf_feature1;     /* Standard or configuration ?  */
        unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
        unsigned char mpf_feature3;     /* Unused (0)                   */
        unsigned char mpf_feature4;     /* Unused (0)                   */
        unsigned char mpf_feature5;     /* Unused (0)                   */
 };
 
+#define MPC_SIGNATURE "PCMP"
+
 struct mp_config_table
 {
        char mpc_signature[4];
-#define MPC_SIGNATURE "PCMP"
        unsigned short mpc_length;      /* Size of table */
        char  mpc_spec;                 /* 0x01 */
        char  mpc_checksum;
        char  mpc_oem[8];
        char  mpc_productid[12];
-       unsigned long mpc_oemptr;       /* 0 if not present */
+       unsigned int mpc_oemptr;        /* 0 if not present */
        unsigned short mpc_oemsize;     /* 0 if not present */
        unsigned short mpc_oemcount;
-       unsigned long mpc_lapic;        /* APIC address */
-       unsigned long reserved;
+       unsigned int mpc_lapic; /* APIC address */
+       unsigned int reserved;
 };
 
 /* Followed by entries */
 
-#define        MP_PROCESSOR    0
-#define        MP_BUS          1
-#define        MP_IOAPIC       2
-#define        MP_INTSRC       3
-#define        MP_LINTSRC      4
-#define        MP_TRANSLATION  192  /* Used by IBM NUMA-Q to describe node 
locality */
+#define        MP_PROCESSOR            0
+#define        MP_BUS                  1
+#define        MP_IOAPIC               2
+#define        MP_INTSRC               3
+#define        MP_LINTSRC              4
+/* Used by IBM NUMA-Q to describe node locality */
+#define        MP_TRANSLATION          192
+
+#define CPU_ENABLED            1       /* Processor is available */
+#define CPU_BOOTPROCESSOR      2       /* Processor is the BP */
+
+#define CPU_STEPPING_MASK      0x000F
+#define CPU_MODEL_MASK         0x00F0
+#define CPU_FAMILY_MASK                0x0F00
 
 struct mpc_config_processor
 {
@@ -61,14 +77,9 @@ struct mpc_config_processor
        unsigned char mpc_apicid;       /* Local APIC number */
        unsigned char mpc_apicver;      /* Its versions */
        unsigned char mpc_cpuflag;
-#define CPU_ENABLED            1       /* Processor is available */
-#define CPU_BOOTPROCESSOR      2       /* Processor is the BP */
-       unsigned long mpc_cpufeature;           
-#define CPU_STEPPING_MASK 0x0F
-#define CPU_MODEL_MASK 0xF0
-#define CPU_FAMILY_MASK        0xF00
-       unsigned long mpc_featureflag;  /* CPUID feature value */
-       unsigned long mpc_reserved[2];
+       unsigned int mpc_cpufeature;
+       unsigned int mpc_featureflag;   /* CPUID feature value */
+       unsigned int mpc_reserved[2];
 };
 
 struct mpc_config_bus
@@ -98,14 +109,15 @@ struct mpc_config_bus
 #define BUSTYPE_VME    "VME"
 #define BUSTYPE_XPRESS "XPRESS"
 
+#define MPC_APIC_USABLE                0x01
+
 struct mpc_config_ioapic
 {
        unsigned char mpc_type;
        unsigned char mpc_apicid;
        unsigned char mpc_apicver;
        unsigned char mpc_flags;
-#define MPC_APIC_USABLE                0x01
-       unsigned long mpc_apicaddr;
+       unsigned int mpc_apicaddr;
 };
 
 struct mpc_config_intsrc
@@ -130,6 +142,7 @@ enum mp_irq_source_types {
 #define MP_IRQDIR_HIGH         1
 #define MP_IRQDIR_LOW          3
 
+#define MP_APIC_ALL    0xFF
 
 struct mpc_config_lintsrc
 {
@@ -138,15 +151,15 @@ struct mpc_config_lintsrc
        unsigned short mpc_irqflag;
        unsigned char mpc_srcbusid;
        unsigned char mpc_srcbusirq;
-       unsigned char mpc_destapic;     
-#define MP_APIC_ALL    0xFF
+       unsigned char mpc_destapic;
        unsigned char mpc_destapiclint;
 };
 
+#define MPC_OEM_SIGNATURE "_OEM"
+
 struct mp_config_oemtable
 {
        char oem_signature[4];
-#define MPC_OEM_SIGNATURE "_OEM"
        unsigned short oem_length;      /* Size of table */
        char  oem_rev;                  /* 0x01 */
        char  oem_checksum;
@@ -155,13 +168,13 @@ struct mp_config_oemtable
 
 struct mpc_config_translation
 {
-        unsigned char mpc_type;
-        unsigned char trans_len;
-        unsigned char trans_type;
-        unsigned char trans_quad;
-        unsigned char trans_global;
-        unsigned char trans_local;
-        unsigned short trans_reserved;
+       unsigned char mpc_type;
+       unsigned char trans_len;
+       unsigned char trans_type;
+       unsigned char trans_quad;
+       unsigned char trans_global;
+       unsigned char trans_local;
+       unsigned short trans_reserved;
 };
 
 /*
-
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