Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=de4218634e3df6d73a3e6cdfdf3a17fa3bc7e013
Commit:     de4218634e3df6d73a3e6cdfdf3a17fa3bc7e013
Parent:     27efeb67714608b28c0b213cceb6080749435c6b
Author:     Andi Kleen <[EMAIL PROTECTED]>
AuthorDate: Wed Jan 30 13:32:37 2008 +0100
Committer:  Ingo Molnar <[EMAIL PROTECTED]>
CommitDate: Wed Jan 30 13:32:37 2008 +0100

    x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs
    
    According to AMD RDTSC can be synchronized through MFENCE.
    Implement the necessary CPUID bit for that.
    
    Cc: [EMAIL PROTECTED]
    Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
    Signed-off-by: Ingo Molnar <[EMAIL PROTECTED]>
    Signed-off-by: Thomas Gleixner <[EMAIL PROTECTED]>
---
 arch/x86/kernel/cpu/amd.c    |    3 +++
 arch/x86/kernel/setup_64.c   |    4 ++--
 include/asm-x86/cpufeature.h |    1 +
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1ff88c7..aaa8101 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -301,6 +301,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        /* K6s reports MCEs but don't actually have all the MSRs */
        if (c->x86 < 6)
                clear_bit(X86_FEATURE_MCE, c->x86_capability);
+
+       if (cpu_has_xmm)
+               set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
 }
 
 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned 
int size)
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 0240910..2139aa6 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -746,8 +746,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
                set_cpu_cap(c, X86_FEATURE_K8);
 
-       /* RDTSC can be speculated around */
-       clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
+       /* MFENCE stops RDTSC speculation */
+       set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 
        /* Family 10 doesn't support C states in MWAIT so don't use it */
        if (c->x86 == 0x10 && !force_mwait)
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 75e2f78..7d53eea 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -79,6 +79,7 @@
 /* 14 free */
 #define X86_FEATURE_SYNC_RDTSC (3*32+15)  /* RDTSC synchronizes the CPU */
 #define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well on this 
CPU */
+#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */
-
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