Commit:     32c7553f824d0d76771404f0e11d6059f82e8de7
Parent:     51fc97b93545e71cec578d6771bceeb92bc2d50b
Author:     Andi Kleen <[EMAIL PROTECTED]>
AuthorDate: Wed Jan 30 13:32:41 2008 +0100
Committer:  Ingo Molnar <[EMAIL PROTECTED]>
CommitDate: Wed Jan 30 13:32:41 2008 +0100

    x86: remove explicit C3 TSC check on 64bit
    Trust the ACPI code to disable TSC instead when C3 is used.
    AMD Fam10h does not disable TSC in any C states so the
    check was incorrect there anyways after the change
    to handle this like Intel on AMD too.
    This allows to use the TSC when C3 is disabled in software
    (acpi.max_c_state=2), but the BIOS supports it anyways.
    Match i386 behaviour.
    Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
    Signed-off-by: Ingo Molnar <[EMAIL PROTECTED]>
    Signed-off-by: Thomas Gleixner <[EMAIL PROTECTED]>
 arch/x86/kernel/tsc_64.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
index 322b38c..c62f3b6 100644
--- a/arch/x86/kernel/tsc_64.c
+++ b/arch/x86/kernel/tsc_64.c
@@ -273,15 +273,8 @@ __cpuinit int unsynchronized_tsc(void)
                return 1;
-       if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
-               /* But TSC doesn't tick in C3 so don't use it there */
-               if (acpi_gbl_FADT.header.length > 0 &&
-                   acpi_gbl_FADT.C3latency < 1000)
-                       return 1;
+       if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
                return 0;
-       }
        /* Assume multi socket systems are not synchronized */
        return num_present_cpus() > 1;
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