Commit:     51fc97b93545e71cec578d6771bceeb92bc2d50b
Parent:     2b16a2353814a513cdb5c5c739b76a19d7ea39ce
Author:     Andi Kleen <[EMAIL PROTECTED]>
AuthorDate: Wed Jan 30 13:32:40 2008 +0100
Committer:  Ingo Molnar <[EMAIL PROTECTED]>
CommitDate: Wed Jan 30 13:32:40 2008 +0100

    x86: allow TSC clock source on AMD Fam10h and some cleanup
    After a lot of discussions with AMD it turns out that TSC
    on Fam10h CPUs is synchronized when the CONSTANT_TSC cpuid bit is set.
    Or rather that if there are ever systems where that is not
    true it would be their BIOS' task to disable the bit.
    So finally use TSC gettimeofday on Fam10h by default.
    Or rather it is always used now on CPUs where the AMD
    specific CONSTANT_TSC bit is set.
    This gives a nice speed bost for gettimeofday() on these systems
    which tends to be by far the most common v/syscall.
    On a Fam10h system here TSC gtod uses about 20% of the CPU time of
    acpi_pm based gtod(). This was measured on 32bit, on 64bit
    it is even better because TSC gtod() can use a vsyscall
    and stay in ring 3, which acpi_pm doesn't.
    The Intel check simply checks for CONSTANT_TSC too without hardcoding
    Intel vendor. This is equivalent on 64bit because all 64bit capable Intel
    CPUs will have CONSTANT_TSC set.
    On Intel there is no CPU supplied CONSTANT_TSC bit currently,
    but we synthesize one based on hardcoded knowledge which steppings
    have p-state invariant TSC.
    So the new logic is now: On CPUs which have the AMD specific
    CONSTANT_TSC bit set or on Intel CPUs which are new enough
    to be known to have p-state invariant TSC always use
    TSC based gettimeofday()
    Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
    Signed-off-by: Ingo Molnar <[EMAIL PROTECTED]>
    Signed-off-by: Thomas Gleixner <[EMAIL PROTECTED]>
 arch/x86/kernel/tsc_32.c |    5 +++++
 arch/x86/kernel/tsc_64.c |    5 ++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/tsc_32.c b/arch/x86/kernel/tsc_32.c
index 00bb4c1..2a7b95b 100644
--- a/arch/x86/kernel/tsc_32.c
+++ b/arch/x86/kernel/tsc_32.c
@@ -354,6 +354,11 @@ __cpuinit int unsynchronized_tsc(void)
        if (!cpu_has_tsc || tsc_unstable)
                return 1;
+       /* Anything with constant TSC should be synchronized */
+       if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
+               return 0;
         * Intel systems are normally all synchronized.
         * Exceptions must mark TSC as unstable:
diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
index 2cc55b7..322b38c 100644
--- a/arch/x86/kernel/tsc_64.c
+++ b/arch/x86/kernel/tsc_64.c
@@ -272,9 +272,8 @@ __cpuinit int unsynchronized_tsc(void)
        if (apic_is_clustered_box())
                return 1;
-       /* Most intel systems have synchronized TSCs except for
-          multi node systems */
-       if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
+       if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
                /* But TSC doesn't tick in C3 so don't use it there */
                if (acpi_gbl_FADT.header.length > 0 &&
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