Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=2af59f7d5c3e342db4bdd28c59090aee05577aef
Commit:     2af59f7d5c3e342db4bdd28c59090aee05577aef
Parent:     5834584e4ea0b03c767e315a5879551b240c5652
Author:     Matthias Fuchs <[EMAIL PROTECTED]>
AuthorDate: Fri Dec 7 09:23:05 2007 +1100
Committer:  Josh Boyer <[EMAIL PROTECTED]>
CommitDate: Tue Jan 8 07:58:09 2008 -0600

    [POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper
    
    This patch adds support for 405GPr processors with optional
    new mode strapping. ibm405gp_fixup_clocks() can now be used
    for 405GP and 405GPr CPUs.
    
    This is in preparation of porting the cpci405 platform support
    from arch/ppc to arch/powerpc.
    
    This patch also adds ibm405ep_fixup_clocks() to support
    405EP CPUs from the boot wrapper.
    
    Signed-off-by: Matthias Fuchs <[EMAIL PROTECTED]>
    Signed-off-by: Josh Boyer <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/4xx.c |   81 ++++++++++++++++++++++++++++++++++++++++++----
 arch/powerpc/boot/4xx.h |    1 +
 arch/powerpc/boot/dcr.h |    5 +++
 3 files changed, 80 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 33f25b6..61a4045 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -499,20 +499,45 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned 
int ser_clk)
        u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
        u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
        u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
+       u32 psr = mfdcr(DCRN_405_CPC0_PSR);
        u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
-       u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
+       u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
 
        fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
        fbdv = (pllmr & 0x1e000000) >> 25;
-       cbdv = ((pllmr & 0x00060000) >> 17) + 1;
-       opdv = ((pllmr & 0x00018000) >> 15) + 1;
-       epdv = ((pllmr & 0x00001800) >> 13) + 2;
+       if (fbdv == 0)
+               fbdv = 16;
+       cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
+       opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
+       ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
+       epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
        udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
 
-       m = fwdv * fbdv * cbdv;
+       /* check for 405GPr */
+       if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
+               fwdvb = 8 - (pllmr & 0x00000007);
+               if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
+                       if (psr & 0x00000020) /* New mode enable */
+                               m = fwdvb * 2 * ppdv;
+                       else
+                               m = fwdvb * cbdv * ppdv;
+               else if (psr & 0x00000020) /* New mode enable */
+                       if (psr & 0x00000800) /* PerClk synch mode */
+                               m = fwdvb * 2 * epdv;
+                       else
+                               m = fbdv * fwdv;
+               else if (epdv == fbdv)
+                       m = fbdv * cbdv * epdv;
+               else
+                       m = fbdv * fwdvb * cbdv;
 
-       cpu = sys_clk * m / fwdv;
-       plb = cpu / cbdv;
+               cpu = sys_clk * m / fwdv;
+               plb = sys_clk * m / (fwdvb * cbdv);
+       } else {
+               m = fwdv * fbdv * cbdv;
+               cpu = sys_clk * m / fwdv;
+               plb = cpu / cbdv;
+       }
        opb = plb / opdv;
        ebc = plb / epdv;
 
@@ -541,3 +566,45 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned 
int ser_clk)
        dt_fixup_clock("/plb/opb/[EMAIL PROTECTED]", uart1);
 }
 
+
+void ibm405ep_fixup_clocks(unsigned int sys_clk)
+{
+       u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
+       u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
+       u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
+       u32 cpu, plb, opb, ebc, uart0, uart1;
+       u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
+       u32 pllmr0_ccdv, tb, m;
+
+       fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
+       fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
+       fbdv = (pllmr1 & 0x00f00000) >> 20;
+       if (fbdv == 0)
+               fbdv = 16;
+
+       cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
+       epdv = ((pllmr0 & 0x00000300) >> 8) + 2;  /* PLB:EBC */
+       opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
+
+       m = fbdv * fwdvb;
+
+       pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
+       if (pllmr1 & 0x80000000)
+               cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
+       else
+               cpu = sys_clk / pllmr0_ccdv;
+
+       plb = cpu / cbdv;
+       opb = plb / opdv;
+       ebc = plb / epdv;
+       tb = cpu;
+       uart0 = cpu / (cpc0_ucr & 0x0000007f);
+       uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
+
+       dt_fixup_cpu_clocks(cpu, tb, 0);
+       dt_fixup_clock("/plb", plb);
+       dt_fixup_clock("/plb/opb", opb);
+       dt_fixup_clock("/plb/ebc", ebc);
+       dt_fixup_clock("/plb/opb/[EMAIL PROTECTED]", uart0);
+       dt_fixup_clock("/plb/opb/[EMAIL PROTECTED]", uart1);
+}
diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h
index fbe0632..2606e64 100644
--- a/arch/powerpc/boot/4xx.h
+++ b/arch/powerpc/boot/4xx.h
@@ -20,6 +20,7 @@ void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
 void ibm4xx_fixup_ebc_ranges(const char *ebc);
 
 void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
+void ibm405ep_fixup_clocks(unsigned int sys_clk);
 void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
 void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
                           unsigned int tmr_clk);
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 55655f7..95b9f53 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -146,7 +146,12 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, 
SDRAM0_B1CR,
 #define DCRN_CPC0_PLLMR 0xb0
 #define DCRN_405_CPC0_CR0 0xb1
 #define DCRN_405_CPC0_CR1 0xb2
+#define DCRN_405_CPC0_PSR 0xb4
 
+/* 405EP Clocking/Power Management/Chip Control regs */
+#define DCRN_CPC0_PLLMR0  0xf0
+#define DCRN_CPC0_PLLMR1  0xf4
+#define DCRN_CPC0_UCR     0xf5
 
 /* 440GX Clock control etc */
 
-
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