Commit:     1eed29df472a33bba013d5a2ea2f9e32f4414397
Parent:     3c72426f0539c1abce17918d1456f7a6a5a11f90
Author:     Haavard Skinnemoen <[EMAIL PROTECTED]>
AuthorDate: Wed Feb 6 01:38:11 2008 -0800
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Wed Feb 6 10:41:10 2008 -0800

    atmel_spi throughput improvement
    Don't insert (undesirable) delays between consecutive words (DLYBCT) or when
    activating chipselects (DLYBS).
    Removing the between-word delays improves the performance of bulk transfers
    (such as mtd_dataflash, m25p80, mmc_spi) significantly.  In one test, the
    improvement was a factor of more than eight!
    (The large DLYBCT value came from the legacy at91 SPI driver, and it's not
    clear why it used such a huge value.)
    Signed-off-by: Haavard Skinnemoen <[EMAIL PROTECTED]>
    Signed-off-by: David Brownell <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
 drivers/spi/atmel_spi.c |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index ff10808..b09d336 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -490,9 +490,14 @@ static int atmel_spi_setup(struct spi_device *spi)
        if (!(spi->mode & SPI_CPHA))
                csr |= SPI_BIT(NCPHA);
-       /* TODO: DLYBS and DLYBCT */
-       csr |= SPI_BF(DLYBS, 10);
-       csr |= SPI_BF(DLYBCT, 10);
+       /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
+        *
+        * DLYBCT would add delays between words, slowing down transfers.
+        * It could potentially be useful to cope with DMA bottlenecks, but
+        * in those cases it's probably best to just use a lower bitrate.
+        */
+       csr |= SPI_BF(DLYBS, 0);
+       csr |= SPI_BF(DLYBCT, 0);
        /* chipselect must have been muxed as GPIO (e.g. in board setup) */
        npcs_pin = (unsigned int)spi->controller_data;
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