Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=3d5e2c13b13468f5eb2ac9323690af7e17f195fe
Commit:     3d5e2c13b13468f5eb2ac9323690af7e17f195fe
Parent:     576cc458a64673ecf3fa7f1bab751e52fd939071
Author:     Dave Airlie <[EMAIL PROTECTED]>
AuthorDate: Thu Feb 7 15:01:05 2008 +1000
Committer:  Dave Airlie <[EMAIL PROTECTED]>
CommitDate: Thu Feb 7 15:13:40 2008 +1000

    drm: add initial r500 drm support
    
    This adds CP support for the r500 series of chips, and allows
    accel 2D support on these chips with a new radeon driver.
    
    Signed-off-by: Dave Airlie <[EMAIL PROTECTED]>
---
 drivers/char/drm/drm_pciids.h   |   95 +++++++++++++++++++++++++++
 drivers/char/drm/r300_cmdbuf.c  |   39 ++++++++----
 drivers/char/drm/radeon_cp.c    |  135 ++++++++++++++++++++++++++-------------
 drivers/char/drm/radeon_drm.h   |    1 +
 drivers/char/drm/radeon_drv.h   |   26 +++++++-
 drivers/char/drm/radeon_state.c |    3 +
 6 files changed, 240 insertions(+), 59 deletions(-)

diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index c69a4d0..f524688 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -139,6 +139,101 @@
        {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV410|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV410|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV410|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R520|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV515|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV570|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV570|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV570|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV570|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV570|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RV560|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
        {0, 0, 0}
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index 8cd8271..0f4afc4 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -77,23 +77,31 @@ static int r300_emit_cliprects(drm_radeon_private_t 
*dev_priv,
                                return -EFAULT;
                        }
 
-                       box.x1 =
-                           (box.x1 +
-                            R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
-                       box.y1 =
-                           (box.y1 +
-                            R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
-                       box.x2 =
-                           (box.x2 +
-                            R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
-                       box.y2 =
-                           (box.y2 +
-                            R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
+                       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= 
CHIP_RV515) {
+                               box.x1 = (box.x1) &
+                                       R300_CLIPRECT_MASK;
+                               box.y1 = (box.y1) &
+                                       R300_CLIPRECT_MASK;
+                               box.x2 = (box.x2) &
+                                       R300_CLIPRECT_MASK;
+                               box.y2 = (box.y2) &
+                                       R300_CLIPRECT_MASK;
+                       } else {
+                               box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
+                                       R300_CLIPRECT_MASK;
+                               box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
+                                       R300_CLIPRECT_MASK;
+                               box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
+                                       R300_CLIPRECT_MASK;
+                               box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
+                                       R300_CLIPRECT_MASK;
 
+                       }
                        OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
                                 (box.y1 << R300_CLIPRECT_Y_SHIFT));
                        OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
                                 (box.y2 << R300_CLIPRECT_Y_SHIFT));
+
                }
 
                OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
@@ -133,9 +141,11 @@ static int r300_emit_cliprects(drm_radeon_private_t 
*dev_priv,
 
 static u8 r300_reg_flags[0x10000 >> 2];
 
-void r300_init_reg_flags(void)
+void r300_init_reg_flags(struct drm_device *dev)
 {
        int i;
+       drm_radeon_private_t *dev_priv = dev->dev_private;
+
        memset(r300_reg_flags, 0, 0x10000 >> 2);
 #define ADD_RANGE_MARK(reg, count,mark) \
                for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
@@ -230,6 +240,9 @@ void r300_init_reg_flags(void)
        ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
        ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
+               ADD_RANGE(0x4074, 16);
+       }
 }
 
 static __inline__ int r300_check_range(unsigned reg, int count)
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 020323b..5dc799a 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -816,6 +816,46 @@ static const u32 R300_cp_microcode[][2] = {
        {0000000000, 0000000000},
 };
 
+static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+       u32 ret;
+       RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
+       ret = RADEON_READ(R520_MC_IND_DATA);
+       RADEON_WRITE(R520_MC_IND_INDEX, 0);
+       return ret;
+}
+
+u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
+{
+
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+               return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+       else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+               return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
+       else
+               return RADEON_READ(RADEON_MC_FB_LOCATION);
+}
+
+static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 
fb_loc)
+{
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+               RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+       else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+               RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
+       else
+               RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
+}
+
+static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 
agp_loc)
+{
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+               RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+       else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+               RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
+       else
+               RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
+}
+
 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -824,7 +864,7 @@ static int RADEON_READ_PLL(struct drm_device * dev, int 
addr)
        return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 }
 
-static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 {
        RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
        return RADEON_READ(RADEON_PCIE_DATA);
@@ -1074,41 +1114,43 @@ static int radeon_do_engine_reset(struct drm_device * 
dev)
 
        radeon_do_pixcache_flush(dev_priv);
 
-       clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
-       mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
-
-       RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
-                                           RADEON_FORCEON_MCLKA |
-                                           RADEON_FORCEON_MCLKB |
-                                           RADEON_FORCEON_YCLKA |
-                                           RADEON_FORCEON_YCLKB |
-                                           RADEON_FORCEON_MC |
-                                           RADEON_FORCEON_AIC));
-
-       rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
-       RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-                                             RADEON_SOFT_RESET_CP |
-                                             RADEON_SOFT_RESET_HI |
-                                             RADEON_SOFT_RESET_SE |
-                                             RADEON_SOFT_RESET_RE |
-                                             RADEON_SOFT_RESET_PP |
-                                             RADEON_SOFT_RESET_E2 |
-                                             RADEON_SOFT_RESET_RB));
-       RADEON_READ(RADEON_RBBM_SOFT_RESET);
-       RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
-                                             ~(RADEON_SOFT_RESET_CP |
-                                               RADEON_SOFT_RESET_HI |
-                                               RADEON_SOFT_RESET_SE |
-                                               RADEON_SOFT_RESET_RE |
-                                               RADEON_SOFT_RESET_PP |
-                                               RADEON_SOFT_RESET_E2 |
-                                               RADEON_SOFT_RESET_RB)));
-       RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
-       RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
-       RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
-       RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+               clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
+               mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
+
+               RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
+                                                   RADEON_FORCEON_MCLKA |
+                                                   RADEON_FORCEON_MCLKB |
+                                                   RADEON_FORCEON_YCLKA |
+                                                   RADEON_FORCEON_YCLKB |
+                                                   RADEON_FORCEON_MC |
+                                                   RADEON_FORCEON_AIC));
+
+               rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+               RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+                                                     RADEON_SOFT_RESET_CP |
+                                                     RADEON_SOFT_RESET_HI |
+                                                     RADEON_SOFT_RESET_SE |
+                                                     RADEON_SOFT_RESET_RE |
+                                                     RADEON_SOFT_RESET_PP |
+                                                     RADEON_SOFT_RESET_E2 |
+                                                     RADEON_SOFT_RESET_RB));
+               RADEON_READ(RADEON_RBBM_SOFT_RESET);
+               RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+                                                     ~(RADEON_SOFT_RESET_CP |
+                                                       RADEON_SOFT_RESET_HI |
+                                                       RADEON_SOFT_RESET_SE |
+                                                       RADEON_SOFT_RESET_RE |
+                                                       RADEON_SOFT_RESET_PP |
+                                                       RADEON_SOFT_RESET_E2 |
+                                                       RADEON_SOFT_RESET_RB)));
+               RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+               RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
+               RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
+               RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
+       }
 
        /* Reset the CP ring */
        radeon_do_cp_reset(dev_priv);
@@ -1134,14 +1176,14 @@ static void radeon_cp_init_ring_buffer(struct 
drm_device * dev,
         * always appended to the fb which is not necessarily the case
         */
        if (!dev_priv->new_memmap)
-               RADEON_WRITE(RADEON_MC_FB_LOCATION,
+               radeon_write_fb_location(dev_priv,
                             ((dev_priv->gart_vm_start - 1) & 0xffff0000)
                             | (dev_priv->fb_location >> 16));
 
 #if __OS_HAS_AGP
        if (dev_priv->flags & RADEON_IS_AGP) {
                RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
-               RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+               radeon_write_agp_location(dev_priv,
                             (((dev_priv->gart_vm_start - 1 +
                                dev_priv->gart_size) & 0xffff0000) |
                              (dev_priv->gart_vm_start >> 16)));
@@ -1305,7 +1347,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * 
dev_priv, int on)
 
                RADEON_WRITE(RADEON_AGP_BASE, (unsigned 
int)dev_priv->gart_vm_start);
                dev_priv->gart_size = 32*1024*1024;
-               RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+               radeon_write_agp_location(dev_priv,
                             (((dev_priv->gart_vm_start - 1 +
                               dev_priv->gart_size) & 0xffff0000) |
                             (dev_priv->gart_vm_start >> 16)));
@@ -1339,7 +1381,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * 
dev_priv, int on)
                                  dev_priv->gart_vm_start +
                                  dev_priv->gart_size - 1);
 
-               RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
+               radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 
                RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
                                  RADEON_PCIE_TX_GART_EN);
@@ -1382,7 +1424,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * 
dev_priv, int on)
 
                /* Turn off AGP aperture -- is this required for PCI GART?
                 */
-               RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
+               radeon_write_agp_location(dev_priv, 0xffffffc0);
                RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
        } else {
                RADEON_WRITE(RADEON_AIC_CNTL,
@@ -1587,10 +1629,9 @@ static int radeon_do_init_cp(struct drm_device * dev, 
drm_radeon_init_t * init)
                          dev->agp_buffer_map->handle);
        }
 
-       dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
-                                & 0xffff) << 16;
+       dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 
16;
        dev_priv->fb_size =
-               ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
+               ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
                - dev_priv->fb_location;
 
        dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
@@ -1841,7 +1882,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, 
struct drm_file *file_pri
        LOCK_TEST_WITH_RETURN(dev, file_priv);
 
        if (init->func == RADEON_INIT_R300_CP)
-               r300_init_reg_flags();
+               r300_init_reg_flags(dev);
 
        switch (init->func) {
        case RADEON_INIT_CP:
@@ -2250,6 +2291,10 @@ int radeon_driver_load(struct drm_device *dev, unsigned 
long flags)
        case CHIP_R350:
        case CHIP_R420:
        case CHIP_RV410:
+       case CHIP_RV515:
+       case CHIP_R520:
+       case CHIP_RV570:
+       case CHIP_R580:
                dev_priv->flags |= RADEON_HAS_HIERZ;
                break;
        default:
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index 5f8d042..71e5b21 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -656,6 +656,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_SCRATCH_OFFSET        11
 #define RADEON_PARAM_CARD_TYPE             12
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
+#define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 
 typedef struct drm_radeon_getparam {
        int param;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 443a895..4434332 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -123,6 +123,12 @@ enum radeon_family {
        CHIP_R420,
        CHIP_RV410,
        CHIP_RS400,
+       CHIP_RV515,
+       CHIP_R520,
+       CHIP_RV530,
+       CHIP_RV560,
+       CHIP_RV570,
+       CHIP_R580,
        CHIP_LAST,
 };
 
@@ -342,6 +348,7 @@ extern int radeon_cp_resume(struct drm_device *dev, void 
*data, struct drm_file
 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct 
drm_file *file_priv);
 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct 
drm_file *file_priv);
 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct 
drm_file *file_priv);
+extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
 
 extern void radeon_freelist_reset(struct drm_device * dev);
 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
@@ -388,7 +395,7 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned 
int cmd,
                                unsigned long arg);
 
 /* r300_cmdbuf.c */
-extern void r300_init_reg_flags(void);
+extern void r300_init_reg_flags(struct drm_device *dev);
 
 extern int r300_do_cp_cmdbuf(struct drm_device * dev,
                             struct drm_file *file_priv,
@@ -460,6 +467,16 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_IGPGART_ENABLE           0x38
 #define RADEON_IGPGART_UNK_39           0x39
 
+#define R520_MC_IND_INDEX 0x70
+#define R520_MC_IND_WR_EN (1<<24)
+#define R520_MC_IND_DATA  0x74
+
+#define RV515_MC_FB_LOCATION 0x01
+#define RV515_MC_AGP_LOCATION 0x02
+
+#define R520_MC_FB_LOCATION 0x04
+#define R520_MC_AGP_LOCATION 0x05
+
 #define RADEON_MPP_TB_CONFIG           0x01c0
 #define RADEON_MEM_CNTL                        0x0140
 #define RADEON_MEM_SDRAM_MODE_REG      0x0158
@@ -1052,6 +1069,13 @@ do {                                                     
                \
        RADEON_WRITE( RADEON_PCIE_DATA, (val) );                        \
 } while (0)
 
+#define RADEON_WRITE_MCIND( addr, val )                                        
\
+       do {                                                            \
+               RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));    
\
+               RADEON_WRITE(R520_MC_IND_DATA, (val));                  \
+               RADEON_WRITE(R520_MC_IND_INDEX, 0);     \
+       } while (0)
+
 #define CP_PACKET0( reg, n )                                           \
        (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET0_TABLE( reg, n )                                     \
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 1dffdc3..6f75512 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -3034,6 +3034,9 @@ static int radeon_cp_getparam(struct drm_device *dev, 
void *data, struct drm_fil
        case RADEON_PARAM_VBLANK_CRTC:
                value = radeon_vblank_crtc_get(dev);
                break;
+       case RADEON_PARAM_FB_LOCATION:
+               value = radeon_read_fb_location(dev_priv);
+               break;
        default:
                DRM_DEBUG("Invalid parameter %d\n", param->param);
                return -EINVAL;
-
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