Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=b67360db143448be1f6d68835c6d0cc43837667f
Commit:     b67360db143448be1f6d68835c6d0cc43837667f
Parent:     49883224f6665e2b056fc3e7325b3bba9d1ff2c4
Author:     Chris Zankel <[EMAIL PROTECTED]>
AuthorDate: Thu Sep 6 01:38:18 2007 -0700
Committer:  Chris Zankel <[EMAIL PROTECTED]>
CommitDate: Wed Feb 13 16:58:51 2008 -0800

    [XTENSA] Flush the page-address in update-mmu instead of user-address
    
    The TLB entry for the user address doesn't exist at the time we
    want to flush the caches, so use the page address. Note that processor
    configurations with cache-aliasing issues are treated separately.
    
    Signed-off-by: Chris Zankel <[EMAIL PROTECTED]>
---
 arch/xtensa/mm/cache.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 42bfb69..3ba990c 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -180,9 +180,9 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long 
addr, pte_t pte)
 #else
        if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
            && (vma->vm_flags & VM_EXEC) != 0) {
-               unsigned long vaddr = addr & PAGE_MASK;
-               __flush_dcache_page(vaddr);
-               __invalidate_icache_page(vaddr);
+               unsigned long paddr = (unsigned long) page_address(page);
+               __flush_dcache_page(paddr);
+               __invalidate_icache_page(paddr);
                set_bit(PG_arch_1, &page->flags);
        }
 #endif
-
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