Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=0b2c3afdaaaa3e577300b2235df43eb8af00020b
Commit: 0b2c3afdaaaa3e577300b2235df43eb8af00020b
Parent: 70e137eb48f62e59dfa5e06d0d01f123e9464f9a
Author: Chris Zankel <[EMAIL PROTECTED]>
AuthorDate: Tue Feb 12 10:11:45 2008 -0800
Committer: Chris Zankel <[EMAIL PROTECTED]>
CommitDate: Wed Feb 13 17:08:18 2008 -0800
[XTENSA] Fix icache flush for cache aliasing
Set the execution bit in the temporary TLB when we flush the
instruction cache.
Signed-off-by: Chris Zankel <[EMAIL PROTECTED]>
---
arch/xtensa/mm/misc.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index e1f8803..c885664 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -295,7 +295,7 @@ ENTRY(__tlbtemp_mapping_itlb)
ENTRY(__invalidate_icache_page_alias)
entry sp, 16
- addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
+ addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
mov a4, a2
witlb a6, a2
isync
-
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