Commit:     de6b03456e2e11cbff9f4bb147177374b260d04e
Parent:     03dfa442e5aaf644bb9b3b506abbd76786867eb1
Author:     Chris Zankel <[EMAIL PROTECTED]>
AuthorDate: Wed Dec 19 10:21:50 2007 -0800
Committer:  Chris Zankel <[EMAIL PROTECTED]>
CommitDate: Wed Feb 13 17:24:47 2008 -0800

    [XTENSA] Add volatile keyword to asm statements accessing counter registers
    The compiler get's sometimes to smart and doesn't reread the
    counter registers and the kernel doesn't schedule until the
    counter wraps around.
    Signed-off-by: Chris Zankel <[EMAIL PROTECTED]>
 include/asm-xtensa/timex.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h
index a5fca59..b83a818 100644
--- a/include/asm-xtensa/timex.h
+++ b/include/asm-xtensa/timex.h
@@ -63,10 +63,10 @@ extern cycles_t cacheflush_time;
  * Register access.
-#define WSR_CCOUNT(r)    __asm__("wsr %0,"__stringify(CCOUNT) :: "a" (r))
-#define RSR_CCOUNT(r)    __asm__("rsr %0,"__stringify(CCOUNT) : "=a" (r))
-#define WSR_CCOMPARE(x,r) __asm__("wsr 
%0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
-#define RSR_CCOMPARE(x,r) __asm__("rsr 
%0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
+#define WSR_CCOUNT(r)    asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r))
+#define RSR_CCOUNT(r)    asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r))
+#define WSR_CCOMPARE(x,r) asm volatile ("wsr 
%0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
+#define RSR_CCOMPARE(x,r) asm volatile ("rsr 
%0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
 static inline unsigned long get_ccount (void)
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