Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=9f8fcf38e8928cccf8c7b32668d146e457f2ccf2
Commit: 9f8fcf38e8928cccf8c7b32668d146e457f2ccf2
Parent: 679262578ba975037901556b2ddc6b17a77cf671
Author: Chris Zankel <[EMAIL PROTECTED]>
AuthorDate: Fri Jan 18 16:15:29 2008 -0800
Committer: Chris Zankel <[EMAIL PROTECTED]>
CommitDate: Wed Feb 13 17:43:26 2008 -0800
[XTENSA] Fix cache flush macro for D$/I$ aliasing/non-aliasing
For configurations that have aliasing in the data cache but
not in the instruction cache, we don't need to flush the
instruction cache. Thus, we didn't define the macros to
flush the instruction cache. Some cache-flush functions,
howerver, were using those macros.
Signed-off-by: Chris Zankel <[EMAIL PROTECTED]>
---
include/asm-xtensa/cacheflush.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h
index b773c57..94c4c53 100644
--- a/include/asm-xtensa/cacheflush.h
+++ b/include/asm-xtensa/cacheflush.h
@@ -70,6 +70,8 @@ extern void __flush_invalidate_dcache_page_alias(unsigned
long, unsigned long);
#endif
#if (ICACHE_WAY_SIZE > PAGE_SIZE)
extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
+#else
+# define __invalidate_icache_page_alias(v,p) do { } while(0)
#endif
/*
-
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