Commit:     f6febccd7f86fbe94858a4a32d9384cc014c9f40
Parent:     4f9d5f4a353440f2265781bfa641587964901861
Author:     Atsushi Nemoto <[EMAIL PROTECTED]>
AuthorDate: Sat Feb 23 15:23:39 2008 -0800
Committer:  Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Sat Feb 23 17:12:14 2008 -0800

    atmel_spi: fix clock polarity
    The atmel_spi driver does not initialize clock polarity correctly (except 
    at91rm9200 CS0 channel) in some case.
    The atmel_spi driver uses gpio-controlled chipselect.  OTOH spi clock signal
    is controlled by CSRn.CPOL bit, but this register controls clock signal
    correctly only in 'real transfer' duration.  At the time of cs_activate()
    call, CSRn.CPOL will be initialized correctly, but the controller do not 
    which channel is to be used next, so clock signal will stay at the inactive
    state of last transfer.  If clock polarity of new transfer and last transfer
    was differ, new transfer will start with wrong clock signal state.
    For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0 or 1
    transfer, the clock signal state at the assertion of chipselect will be low.
    Of course this will violates SPI transfer.
    This patch is short term solution for this problem.  It makes all CSRn.CPOL
    match for the transfer before activating chipselect.  For longer term, the
    best fix might be to let NPCS0 stay selected permanently in MR and overwrite
    CSR0 with to the new slave's settings before asserting CS.
    Signed-off-by: Atsushi Nemoto <[EMAIL PROTECTED]>
    Acked-by: Haavard Skinnemoen <[EMAIL PROTECTED]>
    Cc: David Brownell <[EMAIL PROTECTED]>
    Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
    Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
 drivers/spi/atmel_spi.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 293b7ca..85687aa 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -87,6 +87,16 @@ static void cs_activate(struct atmel_spi *as, struct 
spi_device *spi)
        unsigned gpio = (unsigned) spi->controller_data;
        unsigned active = spi->mode & SPI_CS_HIGH;
        u32 mr;
+       int i;
+       u32 csr;
+       u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
+       /* Make sure clock polarity is correct */
+       for (i = 0; i < spi->master->num_chipselect; i++) {
+               csr = spi_readl(as, CSR0 + 4 * i);
+               if ((csr ^ cpol) & SPI_BIT(CPOL))
+                       spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
+       }
        mr = spi_readl(as, MR);
        mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
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