Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=12c247a6719987aad65f83158d2bb3e73c75c1f5
Commit:     12c247a6719987aad65f83158d2bb3e73c75c1f5
Parent:     03994f01e8b72b3d01fd3d09d1cc7c9f421a727c
Author:     Mikael Pettersson <[EMAIL PROTECTED]>
AuthorDate: Sun Feb 24 18:27:03 2008 +0100
Committer:  Ingo Molnar <[EMAIL PROTECTED]>
CommitDate: Tue Feb 26 12:56:04 2008 +0100

    x86: fix boot failure on 486 due to TSC breakage
    
     > Diffing dmesg between git7 and git8 doesn't sched any light since
     > git8 also removed the printouts of the x86 caps as they were being
     > initialised and updated. I'm currently adding those printouts back
     > in the hope of seeing where and when the caps get broken.
    
    That turned out to be very illuminating:
    
     --- dmesg-2.6.24-git7      2008-02-24 18:01:25.295851000 +0100
     +++ dmesg-2.6.24-git8      2008-02-24 18:01:25.530358000 +0100
     ...
     CPU: After generic identify, caps: 00000003 00000000 00000000 00000000 
00000000 00000000 00000000 00000000
    
     CPU: After all inits, caps: 00000003 00000000 00000000 00000000 00000000 
00000000 00000000 00000000
    +CPU: After applying cleared_cpu_caps, caps: 00000013 00000000 00000000 
00000000 00000000 00000000 00000000 00000000
    
    Notice how the TSC cap bit goes from Off to On.
    
    (The first two lines are printout loops from -git7 forward-ported
    to -git8, the third line is the same printout loop added just after
    the xor-with-cleared_cpu_caps[] loop.)
    
    Here's how the breakage occurs:
    1. arch/x86/kernel/tsc_32.c:tsc_init() sees !cpu_has_tsc,
       so bails and calls setup_clear_cpu_cap(X86_FEATURE_TSC).
    2. include/asm-x86/cpufeature.h:setup_clear_cpu_cap(bit) clears
       the bit in boot_cpu_data and sets it in cleared_cpu_caps
    3. arch/x86/kernel/cpu/common.c:identify_cpu() XORs all caps
       in with cleared_cpu_caps
       HOWEVER, at this point c->x86_capability correctly has TSC
       Off, cleared_cpu_caps has TSC On, so the XOR incorrectly
       sets TSC to On in c->x86_capability, with disastrous results.
    
    The real bug is that clearing bits with XOR only works if the
    bits are known to be 1 prior to the XOR, and that's not true here.
    
    A simple fix is to convert the XOR to AND-NOT instead. The following
    patch does that, and allows my 486 to boot 2.6.25-rc kernels again.
    
    [ [EMAIL PROTECTED]: fixed a similar bug in setup_64.c as well. ]
    
    The breakage was introduced via commit 7d851c8d3db0.
    
    Signed-off-by: Mikael Pettersson <[EMAIL PROTECTED]>
    Signed-off-by: Ingo Molnar <[EMAIL PROTECTED]>
---
 arch/x86/kernel/cpu/common.c |    2 +-
 arch/x86/kernel/setup_64.c   |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index f86a3c4..a38aafa 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -504,7 +504,7 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 
        /* Clear all flags overriden by options */
        for (i = 0; i < NCAPINTS; i++)
-               c->x86_capability[i] ^= cleared_cpu_caps[i];
+               c->x86_capability[i] &= ~cleared_cpu_caps[i];
 
        /* Init Machine Check Exception if available. */
        mcheck_init(c);
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 6fd804f..7637dc9 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -1021,7 +1021,7 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 
        /* Clear all flags overriden by options */
        for (i = 0; i < NCAPINTS; i++)
-               c->x86_capability[i] ^= cleared_cpu_caps[i];
+               c->x86_capability[i] &= ~cleared_cpu_caps[i];
 
 #ifdef CONFIG_X86_MCE
        mcheck_init(c);
-
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