#3557: CPU Vector instructions in GHC.Prim
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Reporter: guest | Owner:
Type: feature request | Status: patch
Priority: normal | Milestone: _|_
Component: Compiler (NCG) | Version: 6.11
Keywords: | Testcase:
Blockedby: | Difficulty: Unknown
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
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Comment(by erikd):
I've just done a bit of experimentation on this and with one minor
modification of the LLVM AST implementation (I will make a separate bug
for this) , the LLVM backend can support a number of standard operations
on arbitrarily sized vectors of the standard data types. The only caveat
is that the size of these vectors must be known at compile time.
This suggests that for vectors of a statically known length, operation
like addition could just be passed through to the LLVM backend as a vector
addition primop like:
{{{
vectorAdd :: Vec vsize vtype -> Vector vsize vtype -> Vector vsize vtype
}}}
For platforms where vector operations aren't supported, the LLVM backend
for that platform would be responsible for unrolling the vector operation.
For cases where the the vector width is known only at run time, vector
operations can still be generated by generating a loop using the vector
instructions.
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3557#comment:45>
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