T> Add MIPS32R2 RDHWR-based cycle counter support. T> Does that work in user mode for all *nix ports?
don't know. basing on a quick grep: openbsd, freebsd seem to only allow ULR but never CC/CCRes; netbsd seems to enable everything in HWREna including CC, CCRes. T> Does it not also work in r3, r4, r5? And r6? the instruction and CP0 HWREna are defined in r3, r5, r6 too. there is no r4. T> Is there are mipsisa64 counterpart? mips arch specs list mips32r2+ only where they usually mention mips64 too however i6400, p6600 (64-bit r6 cores) specs say rdhwr and the corresponding hwrena bits are supported. octeon cores has this 32-counter since octeon plus at least as well as a custom 64-bit counter. _______________________________________________ gmp-devel mailing list gmp-devel@gmplib.org https://gmplib.org/mailman/listinfo/gmp-devel