Hi Al.
On Mon, Sep 22, 2014 at 09:12:56PM -0400, al davis wrote:
> > const std::string COMPONENT::port_value(int i)const
> > {
> > assert(_n);
> > assert(i >= 0);
> > assert(i < net_nodes()); // <- boom
> > return _n[i].short_label();
> > }
>
> This code is correct.
>
> i >= net_nodes() is not valid here.
ok. and actually not required, after the DEV_SUBCKT::max_nodes() fix.
> [..]
> > - change max_nodes() in DEV_SUBCKT to
> > {if(_parent){ return _parent->net_nodes();}else{return
> > PORTS_PER_SUBCKT;}}
>
> I think you are correct. The max_nodes() of the offspring is
> the actual net_nodes() of the parent.
thanks for the analysis
> You didn't post the test case. My conclusion of what it was
> .... In Verilog syntax, a user error, entering a node by name,
> with a name that doesn't exist. It runs past the real end of
> the list searching for it.
the test case is a unit test of the gnucap-geda package.
last time i had compiled gnucap with NDEBUG defined...
but you are right. the following also triggers the error.
verilog
module test(n,p);
endmodule
test t(.n(1), .p(0), .q(2));
end
cheers
felix
_______________________________________________
Gnucap-devel mailing list
[email protected]
https://lists.gnu.org/mailman/listinfo/gnucap-devel
