hello, i am interested to do some simple simulations (gates, flip flops, memories) with verilog. I saw there is a repo
gnucap-modelgen-verilog is it possible to load verilog testbench with gnucap? thanks a lot! patrick _______________________________________________ Gnucap-devel mailing list [email protected] https://lists.gnu.org/mailman/listinfo/gnucap-devel
