Hi,
On 05/17/2013 01:40 AM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
> Hello, all. I've changed in arm branch to detect cache type on runtime
> rather than compile time. Now a version compiled for armv6 should work
> on armv7 as well thus avoiding the need of two separate binaries. As an
> additional bonus it doesn't #error anymore when compiled with default
> gcc target (which is armv4t). Please test on armv7 when compiling for
> armv4t, armv6 and armv7.
A couple of minor issues in the cache probe function.
1) In the Main ID Register, for both ARMv6 and ARMv7, bits 15 to 4
contain the primary part number, whose value is implementation defined.
The special values 0x0 and 0x7 of the top 4 bits of the primary part
number are valid only for ARM implementations, i.e. when bits 31 to 24
contain the implementer code 0x41. I don't think we want to restrict
support to ARM implementations only, so I would drop the checks on bits
15 to 12.
2) The Cache Type Register in ARMv7 has always its 4 most significant
bits set to 1000.
So, please consider applying below patch.
Thanks,
Francesco
=== modified file 'grub-core/kern/arm/cache.c'
--- grub-core/kern/arm/cache.c 2013-05-17 11:05:28 +0000
+++ grub-core/kern/arm/cache.c 2013-05-19 14:43:23 +0000
@@ -29,8 +29,7 @@
/* Read main ID Register */
asm volatile ("mrc p15, 0, %0, c0, c0, 0": "=r"(main_id));
- if (((main_id >> 12) & 0xf) == 0x0 || ((main_id >> 12) & 0xf) == 0x7
- || (((main_id >> 16) & 0x7) != 0x7))
+ if (((main_id >> 16) & 0x7) != 0x7)
grub_fatal ("Unsupported ARM ID 0x%x", main_id);
/* Read Cache Type Register */
@@ -56,7 +55,7 @@
grub_arch_cache_ilinesz = 8 << (cache_type & 3);
type = ARCH_ARMV6;
break;
- case 0x80 ... 0x9f:
+ case 0x80 ... 0x8f:
grub_arch_cache_dlinesz = 4 << ((cache_type >> 16) & 0xf);
grub_arch_cache_ilinesz = 4 << (cache_type & 0xf);
type = ARCH_ARMV7;
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