Hi Shea, sorry for the delay.

Shea Levy <s...@shealevy.com> writes:
> * module/system/base/target.scm (cpu-endianness): Add case for "riscv"
> variants.

Applied in commit 08bb4628369cf3efe7c96a32919705c41a9ed9e9 of the
stable-2.2 branch, so it will be included in Guile-2.2.4.

Thank you for working on RISC-V.  That project gives me hope :)

     Mark

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