* gnu/packages/fpga.scm (iverilog): New variable.
---
gnu/packages/fpga.scm | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 7571f87..b0d4819 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -81,3 +81,30 @@ and formal verification.")
;; FIXME use license: MIT Modern variant as described in:
;; <https://fedoraproject.org/wiki/Licensing:MIT>
(license license:expat))))
+
+(define-public iverilog
+ (package
+ (name "iverilog")
+ (version "10.1.1")
+ (source (origin
+ (method url-fetch)
+ (uri
+ (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/verilog-"; version ".tar.gz"))
+ (sha256
+ (base32
+ "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
+ (build-system gnu-build-system)
+ (native-inputs
+ `(("flex" ,flex)
+ ("bison" ,bison)
+ ("ghostscript" ,ghostscript) #| ps2pdf |#))
+ (home-page "http://iverilog.icarus.com/";)
+ (synopsis "FPGA Verilog Simulation and Synthesis Tool")
+ (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+It operates as a compiler, compiling source code written in Verilog
+(IEEE-1364) into some target format.
+For batch simulation, the compiler can generate an intermediate form called
+vvp assembly.
+This intermediate form is executed by the ``vvp'' command.
+For synthesis, the compiler generates netlists in the desired format.")
+ (license license:gpl2)))
