On 12 October 2016 at 13:32, Frank Kleinewoerdemann <frankk.w...@gmail.com>
> the solder joints on the U20 and the NXP TQFP package look tip-top.
Better than on the X3 crystal ;-)
> I got the signals of P81(/WP), P82(/HOLD) and P68(/CS) into the logic
analyzer. Set the trigger to /CS falling edge.
> On hackrf_spi flash write, the /HOLD and /WP are high level throughout
the write process. The /CS signal is changing only during the first phase
of a bock write and remains active low for the remainder of the block write
period after the MOSI signal had activity. The rising edge of SCK is neatly
aligned with stable MISO and MOSI signals.
> Upon /RESET: the SCK rising edge seems to be mis-aligned to MISO and MOSI
signals i.e. the rising edge of SCK is aligned with the rising/falling edge
of MISO/MOSI. The /WP and /HOLD line have transitions on them while /CS is
active low (apart from some transitions right after /RESET -> high). The
/CS, /HOLD and /WP are returned to active high roughly about 2.5ms after
/RESET is active high.
> It's hard to explain. There's too much going on. Can I upload the logic
analyzer capture file for discussion somewhere (its in saleae format)?

I'm not certain, but I believe that the LPC4320 reads the firmware from U20
using quad SPI flash rather than regular SPI at boot time.

> On hackrf_spiflash -r <filename>: Neither SCK nor /CS are driven. At
least the logic analyzer can't trigger on either of them.
> Perhaps an issue with the firmware to set the SPI port for read operation?

I think the issue is a bad SPI flash chip (U20).  Could you contact me off
list with the details of where you bought the HackRF?


> On Sun, Oct 9, 2016 at 11:45 AM, Dominic Spill <domini...@gmail.com>
>> On 8 October 2016 at 22:34, Frank Kleinewoerdemann <frankk.w...@gmail.com>
>> > On Sat, Oct 8, 2016 at 6:25 PM, Dominic Spill <domini...@gmail.com>
>> >>
>> >> > There is also SPI data after reset/reboot but it's not what was
sent to the SPI flash and the clock signal in relation to MOSI/MISO looks
rather odd (like misaligned...clock rising edge vs.stable level on
MISO/MOSI). I can't tell though whether this is expected or not.
>> >>
>> >> What are the WP and HOLD lines doing while you measure this?
>> >
>> > FK: According to the schematic those signals are not on any header or
test point. I'll solder some wires on U20 and advise. Haven't done so yet
as this will probably void any warranty I may have..... IANAL
>> There's really no need to do this, I was just curious.
>> >> Instead of using the logic analyzer, could you write firmware to
flash from DFU mode (hackrf_spiflash -w <filename>) and then, without
resetting, attempt to read it back using hackrf_spiflash -r <new_filename>
?  Then compare those two files to find out if the data is being written to
the flash correctly or not.
>> >
>> > FK: I tried to to read the SPI flash with hackrf_spiflash -r
<filename> but the process hangs after printing 'Reading 256 bytes from
>> > After sending SIGINT to the process, subsequent hackrf_info returns
with 'hackrf_board_id_read() failed: HACKRF_ERROR_LIBUSB (-1000). LED
status is unchanged. Need to reset into DFU mode to recover.
>> It sounds like there is a problem reading and writing to the SPI flash
chip (U20).  The HackRF firmware likely is getting stuck while trying to
read the flash because it's not getting the response that it expects.
>> > Reviewing the tools' code it seems that libusb_control_transfer()
doesn't return. Its timeout parameter is set to 0 so it'll wait forever.
>> > Any idea what could cause this behavior on board level? Would you
think that changing parameters within hackrf.c is worth trying?
>> I don't think any software changes will fix this, it definitely sounds
like a hardware problem.  While I would imagine that it's a problem with
U20 itself rather than the connection to the board, could you take a look
and tell me how the solder joints on U20 look?
>> Dominic
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