On Sat, Apr 14, 2012 at 08:06:00PM +0200, Lukas Tribus wrote: > > You need to pin network interrupts to a specific > > core and have haproxy run on a separate core sharing the same L2 cache as > > the > > one in charge for the interrupts. > > Do recent CPUs like Sandy Bridge and the upcoming Ivy Bridge actually > have shared L2 cache between cores at all? L3 Cache is shared of course, > but Wikipedia [1] suggests Sandy Bridge has a fixed 256 kB L2 cache per > core.
Indeed, many modern CPUs equipped with an L3 cache have per-core L2 cache. Some architectures such as AMD's bulldozer still use shared L2 caches. However, even in these architectures you observe non-uniform architectures. For instance, the AMD 6172 (12-core) has one L2 per core, two memory controllers, one per 6-core. I observed that it was essential to have NIC interrupts and processes running on the same memory controller. My guess is that invlidating a cache line between the two memory controllers requires to pass via the L3 and is much slower. Willy
