Uhh...unless I am just completely off base (and I don't think I am), Intel
PURCHASED most of the cache that was placed on the PII Slot cartridges.
Therefore, it wasn't an issue of yield improvements at all.
Even then, the PII's used two 256KB cache chips, not a single 512KB chip.
Greg
----- Original Message -----
From: "Eli Allen" <[EMAIL PROTECTED]>
To: "The Hardware List" <[email protected]>
Sent: Monday, September 19, 2005 1:11 PM
Subject: Re: [H] New Intel 775 Pin Motherboards
It wasn't so much the die size overall as the PII had a larger die size
overall (had a larger L2 cache then most PPros). It was that the large
single die was harder to produce then 2 smaller dies. With the PPro if
there was a problem with the CPU or the L2 cache both parts hard to be
thrown out, but with the PII they could be tested individually so didn't
have to throw out both.
So the real reason was more to improve the yield more then decrease the
cost of a CPU.
----- Original Message -----
True. However, the size of the die was too large to make it economical
for anything but server usage. (die size = $$$) Plus, the Pentium Pro's
cache, as you state, was not integrated into the core so much as it was
slapped into the die package. Therefore, it couldn't achieve the same
benefits of a huge bus width and low latency that true integrated cache
(first on the Celeron A of all things...) brought.
Greg
