On Sun, Mar 16, 2008 at 11:33:20AM +0000, Oliver Ford wrote: > Kevin O'Connor wrote: >> Also, using the right cache flushing functions is crucial to working >> with "wirq". Is your haret detecting the machine as a pxa (and thus >> using the xscale cache flushes)? >> > Ah yes, that might be it. It is detecting it as a PXA but haret only has > support for the pxa2xx (xscale). I'm not sure how different the caching in > the pxa3xx, which I think is xscale3, is. For one, the xscale3 docs say it > has an L2 cache, although Eric Miao (on the kernel list) says the pxa310 > doesn't, which seems to be correct from poking with the code. This leaves > me a little confused as to what is what.
It looks like there is a different cache flush for xscale3. See arch/arm/mm/proc-xsc3.S. I can bring over the cache function, but I need a reliable way to detect the processor. Do you know of a mechanism? If you have patches for haret, I'd like to see them. Ultimately, we should have one version of haret for all machines. -Kevin _______________________________________________ Haret mailing list [email protected] https://handhelds.org/mailman/listinfo/haret
