Hi everyone,
I tried the way you suggested and copied the files from pxa27x and
renamed them. I found some files in the arm kernel sources, specifically
in arch/mach-pxa/include/mach/hardware.h which contains a mapping of
CPU_ID and cpu type:
...
PXA30x A1 0x69056881 0x1E648013
PXA31x A0 0x69056890 0x0E649013
PXA31x A1 0x69056891 0x1E649013
PXA31x A2 0x69056892 0x2E649013
PXA32x B1 0x69056825 0x5E642013
...
I used these information in the MachinePXA31x::detect() version I wrote.
Apart from this I copied everything from the pxa27x. First I commented
some parts out in preHardwareShutdown and when I tried booting my linux
kernel with this cut down version it reseted my whole windows ce
filesystem, but this could also have been due to a very low battery (I
am not sure whether the filesystem lies in ram or flash).
But after I discovered the dependencies in the c preprocessor macros I
copied them also for the PXA31x.
I attached the patch and I would really like your comments. This is my
first patch and this is also a very naive approach, I admit.
The patch is against a recent svn checkout.
Actually it was an educated guess ;-) as I found this information in the
kernel sources:
#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending
Register */
179 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask
Register */
180 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level
Register */
181 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ
Pending Register */
182 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending
Register */
183 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control
Register */
184
185 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ
Pending Register 2 */
186 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask
Register 2 */
187 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level
Register 2 */
188 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ
Pending Register 2 */
189 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending
Register 2 */
this looked very similar to the Haret Pxa27x part so I gave it a try.
"addlist IRQS p2v(0x40D00000) 0x480 32 0\n"
"addlist IRQS p2v(0x40D0009c) 0xfffffffc 32 0\n"
"addlist IRQS p2v(0x40E00048) 0 32 0\n"
"addlist IRQS p2v(0x40E0004c) 0 32 0\n"
"addlist IRQS p2v(0x40E00050) 0 32 0\n"
"addlist IRQS p2v(0x40E00148) 0 32 0\n"
Watching IRQS and GPIOS seems to work now:
======== Connecting to haret ========
Minimal virtual address: 00010000, maximal virtual address: 7FFFFFFF
Detected machine Generic Intel PXA31x/PXA31x (Plat='PocketPC'
OEM='SGH-i780')
CPU is Intel ARM arch 5TE revision 2 product 9 stepping 1 running in
system mode
Enter 'HELP' for a short command summary.
HaRET(1)# ibit IRQS 26
HaRET(2)# wirq 2
irq:8000a...@a03943f8=80c0c0ec abort:80043...@a03943f0=80c0c110
prefetch:80009...@a03943ec=80c0c13c data=80bcb000
sizes=c:000014e4,t:000454e4
Beginning memory tracing.
Watching IRQS(00): Addr a8d00000(@40d00000)
Watching IRQS(01): Addr a8d0009c(@40d0009c)
Watching IRQS(02): Addr a8e00048(@40e00048)
Watching IRQS(03): Addr a8e0004c(@40e0004c)
Watching IRQS(04): Addr a8e00050(@40e00050)
Watching IRQS(05): Addr a8e00148(@40e00148)
MMU table merging disabled
Replacing windows exception handlers...
Finished installing exception handlers.
000.000(0000000) IRQS a8d00000=4000000
000.000(0000000) IRQS a8d0009c=0
000.000(0000000) IRQS a8e00048=0
000.000(0000000) IRQS a8e0004c=0
000.000(0000000) IRQS a8e00050=0
000.000(0000000) IRQS a8e00148=0
000.323(0000000) IRQS a8e00048(87)=800000
000.580(0000000) IRQS a8e00048(87)=800000
000.785(0000000) IRQS a8e00048(87)=800000
001.000(0000000) IRQS a8e00048(87)=800000
001.308(0000000) IRQS a8e00048(87)=800000
001.344(0000000) IRQS a8e00048(87)=800000
001.501(0000000) IRQS a8e00048(87)=800000
Restoring windows exception handlers...
Finished restoring windows exception handlers.
Handled 2030 irq, 1759 abort, 1625 prefetch, 0 lost, 0 errors
HaRET(2)# watch GPIOS 2
Beginning memory tracing.
Watching GPIOS(00): Addr a8e00000(@40e00000)
Watching GPIOS(01): Addr a8e00004(@40e00004)
Watching GPIOS(02): Addr a8e00008(@40e00008)
Watching GPIOS(03): Addr a8e00100(@40e00100)
Watching GPIOS(04): Addr a8e0000c(@40e0000c)
Watching GPIOS(05): Addr a8e00010(@40e00010)
Watching GPIOS(06): Addr a8e00014(@40e00014)
Watching GPIOS(07): Addr a8e0010c(@40e0010c)
Watching GPIOS(08): Addr a8e00054(@40e00054)
Watching GPIOS(09): Addr a8e00058(@40e00058)
Watching GPIOS(10): Addr a8e0005c(@40e0005c)
Watching GPIOS(11): Addr a8e00060(@40e00060)
Watching GPIOS(12): Addr a8e00064(@40e00064)
Watching GPIOS(13): Addr a8e00068(@40e00068)
Watching GPIOS(14): Addr a8e0006c(@40e0006c)
Watching GPIOS(15): Addr a8e00070(@40e00070)
000.000 GPIOS a8e00000=5107144
000.000 GPIOS a8e00004=0
000.000 GPIOS a8e00008=7d1840
000.000 GPIOS a8e00100=40001dd0
000.000 GPIOS a8e0000c=3d2fa786
000.000 GPIOS a8e00010=fffb8040
000.000 GPIOS a8e00014=fcebdfbf
000.000 GPIOS a8e0010c=fe01817b
000.000 GPIOS a8e00054=0
000.000 GPIOS a8e00058=0
000.000 GPIOS a8e0005c=0
000.000 GPIOS a8e00060=0
000.000 GPIOS a8e00064=0
000.000 GPIOS a8e00068=0
000.000 GPIOS a8e0006c=0
000.000 GPIOS a8e00070=0
001.832 GPIOS a8e00000(23)=5907144
001.950 GPIOS a8e00000(23)=5107144
I am looking forward to your suggestions and comments.
Furthermore, as I was saying I have a linux kernel which boots and
executes a minimal initrd. I found this somewhere on the net, cannot
find it again right now. My problem at the moment is that I have not a
fully usable keyboard on the phone in linux. I cannot access all number
keys which actually usw a special key + letter keys and I cannot enter
some special chars which stopps me from exploring the device and setting
up a network. Everytime I want to try something out I have to write it
to the initrd, copy it to windows boot linux, watch the screen for how
it works out and then take the battery out to reboot into windows.
I am trying to make the usb_ethernet work but the way I have to try is
very cumbersome. Do you have any suggestions on how to get connected to
the phone in some other way which would spare me this procedure?
Marek
Index: src/mach/arch-pxa31x.cpp
===================================================================
RCS file: src/mach/arch-pxa31x.cpp
diff -N src/mach/arch-pxa31x.cpp
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ src/mach/arch-pxa31x.cpp 26 Mar 2009 20:11:03 -0000
@@ -0,0 +1,109 @@
+#include "cpu.h" // DEF_GETCPR
+#include "memory.h" // memPhysMap
+#include "script.h" // runMemScript
+#include "arch-pxa.h"
+#define CONFIG_PXA31x
+#include "pxa2xx.h" // pxaDMA
+
+DEF_GETCPR(get_p15r0, 15, 0, c0, c0, 0)
+
+MachinePXA31x::MachinePXA31x()
+{
+ name = "Generic Intel PXA31x";
+ archname = "PXA31x";
+ dcsr_count = 32;
+}
+
+int
+MachinePXA31x::detect()
+{
+ uint32 p15r0 = get_p15r0();
+ return ((p15r0 >> 24) == 0x69
+ && ((p15r0 >> 12) & 0xff) == 0x56
+ && ((p15r0 >> 4) & 0xff) == 0x89);
+}
+
+void
+MachinePXA31x::init()
+{
+ runMemScript(
+ "set ramaddr 0xa0000000\n"
+ // IRQs
+ "addlist IRQS p2v(0x40D00000) 0x480 32 0\n"
+ "addlist IRQS p2v(0x40D0009c) 0xfffffffc 32 0\n"
+ "addlist IRQS p2v(0x40E00048) 0 32 0\n"
+ "addlist IRQS p2v(0x40E0004c) 0 32 0\n"
+ "addlist IRQS p2v(0x40E00050) 0 32 0\n"
+ "addlist IRQS p2v(0x40E00148) 0 32 0\n"
+ // GPIO levels
+ "addlist GPIOS p2v(0x40E00000)\n"
+ "addlist GPIOS p2v(0x40E00004)\n"
+ "addlist GPIOS p2v(0x40E00008)\n"
+ "addlist GPIOS p2v(0x40E00100)\n"
+ // GPIO directions
+ "addlist GPIOS p2v(0x40E0000C)\n"
+ "addlist GPIOS p2v(0x40E00010)\n"
+ "addlist GPIOS p2v(0x40E00014)\n"
+ "addlist GPIOS p2v(0x40E0010C)\n"
+ // GPIO alt functions
+ "addlist GPIOS p2v(0x40E00054)\n"
+ "addlist GPIOS p2v(0x40E00058)\n"
+ "addlist GPIOS p2v(0x40E0005c)\n"
+ "addlist GPIOS p2v(0x40E00060)\n"
+ "addlist GPIOS p2v(0x40E00064)\n"
+ "addlist GPIOS p2v(0x40E00068)\n"
+ "addlist GPIOS p2v(0x40E0006c)\n"
+ "addlist GPIOS p2v(0x40E00070)\n"
+ // Clock & Power registers
+ "newvar CLOCKS GPIOS 'Architecture clock registers'\n"
+ "addlist CLOCKS p2v(0x41300000)\n" // CCCR
+ "addlist CLOCKS p2v(0x41300004)\n" // CKEN
+ "addlist CLOCKS p2v(0x41300008)\n" // OSCC
+ "addlist CLOCKS p2v(0x4130000C)\n" // CCSR
+ "addlist CLOCKS cp 14 0 6 0 0\n" // CLKCFG
+ "addlist CLOCKS cp 14 0 7 0 0\n" // PWRMODE
+ );
+}
+
+int
+MachinePXA31x::preHardwareShutdown()
+{
+ int ret = MachinePXA::preHardwareShutdown();
+ if (ret)
+ return ret;
+ cken = (uint32 *)memPhysMap(CKEN);
+ uhccoms = (uint32 *)memPhysMap(UHCCOMS);
+ if (! cken || ! uhccoms)
+ return -1;
+ return 0;
+}
+
+// disable USB host.
+static void
+Reset31xUHC(volatile uint32 *uhccoms)
+{
+ // Reset usb host
+ *uhccoms=1;
+}
+
+void
+MachinePXA31x::hardwareShutdown(struct fbinfo *fbi)
+{
+ MachinePXA::hardwareShutdown(fbi);
+ Reset31xUHC(uhccoms);
+
+ *cken=(*cken)&(~(
+// CKEN5_STUART|
+// CKEN6_FFUART|
+// CKEN7_BTUART|
+ CKEN10_USBHOST|
+ CKEN11_USB|
+ CKEN12_MMC|
+ CKEN13_FICP|
+ CKEN19_KEYPAD|
+ CKEN23_SSP1|
+ CKEN24_CAMERA
+ ));
+}
+
+REGMACHINE(MachinePXA31x)
Index: include/arch-pxa.h
===================================================================
RCS file: /cvs/haret/include/arch-pxa.h,v
retrieving revision 1.5
diff -u -8 -p -r1.5 arch-pxa.h
--- include/arch-pxa.h 13 Oct 2007 15:52:35 -0000 1.5
+++ include/arch-pxa.h 26 Mar 2009 20:11:03 -0000
@@ -20,9 +20,23 @@ public:
int detect();
void init();
virtual int preHardwareShutdown();
virtual void hardwareShutdown(struct fbinfo *fbi);
uint32 *cken, *uhccoms;
};
+// PXA 31x
+class MachinePXA31x : public MachinePXA {
+public:
+ MachinePXA31x();
+ int detect();
+ void init();
+ virtual int preHardwareShutdown();
+ virtual void hardwareShutdown(struct fbinfo *fbi);
+
+ uint32 *cken, *uhccoms;
+};
+
+
+
int testPXA();
Index: include/pxa-regs.h
===================================================================
RCS file: /cvs/haret/include/pxa-regs.h,v
retrieving revision 1.1
diff -u -8 -p -r1.1 pxa-regs.h
--- include/pxa-regs.h 12 Nov 2006 06:42:22 -0000 1.1
+++ include/pxa-regs.h 26 Mar 2009 20:11:04 -0000
@@ -2091,17 +2091,19 @@
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
-#ifdef CONFIG_PXA27x
+
+#if defined (CONFIG_PXA27x) || defined (CONFIG_PXA31x)
+
#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
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