Hi,
This time I am selected for GSOC-2018 in Timvideos for the project 'Create
a "Integrated Bit Error Ratio Tester" (iBERT)
<https://github.com/timvideos/getting-started/issues/38>'.
The aim of this project is to create a litescope based "Integrated Bit
Error Ratio Tester" (iBERT) clone. This project has three parts:
a) Data sequence generators + checkers. These generate given bit data
stream, then after transmission and receiving check that the bit data
stream is correct.
b) Data channel wrappers. These give you a common interface to controlling
the parameters of a channel used in transmission and receiving. For simple
data channels this might just provide clock control. For more advanced
channels, like the high speed transceivers, this provides things like
controlling parameters like pre-emphasis, equalisation, etc.
c) Host computer Control GUI / Console. This gives a nice interface for
controlling all the parameters and seeing the results of various tests.
URL of the
1. project proposal
<https://docs.google.com/document/d/1jhVb6CyrWw8kCimvpL75cQcRayJRgqRjzvmZk1r3-zI/edit>
2. Blog <https://gsoc2018blogibert.wordpress.com/>
3. Github username : akhil-123 <https://github.com/akhil-123>
Talking about myself
I am Akhil Singh, a third year B.Tech student from the International
Institute of Information Technology, Hyderabad. My major interests are in
VLSI designing, Embedded Hardware Designing, Digital logic circuits and
Image Processing, machine learning. Apart from academics I am a state level
player of Table tennis and love to play and watch cricket.
Contact details:
Mb. number ; +91-8004948595
Email address : 1997singhak...@gmail.com
akhil.si...@research.iiit.ac.in
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