"Paul D. Smith" <[EMAIL PROTECTED]> wrote in
news:[EMAIL PROTECTED]:
> Without seeing a REAL example of what you're trying to do it's
> difficult to determine how much power you need.
True, true. And I have to support a version of make that doesn't feature
the $(eval) function (Rational's clearmake in GNU compat mode),
unfortunately. I can't even use the $(if) function. Nor $(call).
Ok, here's a totally different example to show exactly what I need to
support (sorry, this is a bit long/detailed). Effectively the same
problem, though (prereq's generated based on target name).
The user will specify programs (exe's) to create in an agreed-upon
variable name called PROGRAMS. e.g.,
PROGRAMS = foo.exe bar.exe .............
Now, the object files (prereqs) that make up (are linked to) each
executable in that list is determined with the following logic, in this
order (will stop at the first that works):
1. check for a variable called <targname>_OFILES. If it exists, use the
objects listed therein. If not, try #2...
2. check for a variable called OFILES. If it exists, use its contents.
If not, use #3.
3. assume there is only one object file that is needed, and its name will
be <targname_prefix>.obj (or .o on Unix). i.e., in the above example,
foo.o is the prereq for foo.exe, and bar.o for bar.exe.
So, if the user sets:
foo.exe_OFILES = a.obj b.obj c.obj
Then the generated targ/prereq line for foo.exe would need to be:
foo.exe : a.obj b.obj c.obj
[commands]
The template that I write to generate the above is of the form:
${PROGRAMS} : ${_OFILES_}
[commands]
_OFILES_ = <logic here to generate correct object prereqs>
Any idea on a clean way to approach this? I'd rather not have to
generate makefiles on the fly to do it, but if that's the only way
(without $(eval), $(if), etc.), I can look into that.
Thanks,
Ernest
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