Hello, I've already searched through the groups but couldn't find the information that I'm looking for. I've some experience with makefiles but I'm not a Guru but I'm pretty sure that there's a commonly used solution for my problem:
We have some dozen modules that are compiled/linked together in different applications. In addition we've contracted some other companies that are providing some additional modules. They are receiving some of the modules in source code, others just as libraries. So for building the same application we have different targets depending on the fact if the modules are available in source code or just as binary. In addition some of the modules are used by all applications, others not. Currently every module is created as a library and has it's own makefile. Every module makefile expands the name and path of the library that it creates to a commonly used macro. The idea is that just by including the modules makefile the set of needed libraries is defined. What I need now is a way to include these module makefiles target dependent. How can this be done? When calling make I don't want to pass an additional variable. Target dependent variable definition doesn't seem to work since they are just defined in the context of the target (but then it's too late to include other makefiles) ... Any hints are welcome! Regards Joerg P.S: I'm sorry for my bad English :-( _______________________________________________ help-gnu-utils mailing list help-gnu-utils@gnu.org http://lists.gnu.org/mailman/listinfo/help-gnu-utils
