Hello,
I have made this post to two different groups but unfortunately I could
not get a solution to my problem. This may be because those groups were
not really concerned with GNU make.
I will write my problem in details that is because I got some unhelpful
advices since what I am trying to do is somehow not ordinary. I want
to compile my source files using MSVC with GNU Make, for the sake of
some kind of portability of course.
Ok, my problem is:
I am trying to handle a software project comprised of several source
and header files. Source and header files are in seperate directories
called "src" and "include" respectively. I want to place my object
files under a seperate directory "obj" and then link those object files
to get the binary under the "out" directory. I want a tidy project
directory. All these directories and makefile will be under a project
directory and make will be executed from this project directory.
Directory structure of the project will be:
proj
|
|- makefile
|- /src
|- /include
|- /obj
|- /out
The makefile that I am using for this is:
all: dirs $(OUTFILE)
$(OUTFILE) : $(OBJECTS)
$(LD) $(LFLAGS) $<
%.obj : %.cpp
@$(CC) $(CFLAGS) $<
.PHONY: dirs
dirs:
[EMAIL PROTECTED] [ ! -d $(OBJ_DIR) ] ; then echo "Creating
$(OBJ_DIR)"; mkdir
$(OBJ_DIR) ; fi
[EMAIL PROTECTED] [ ! -d $(OUT_DIR) ] ; then echo "Creating
$(OUT_DIR)"; mkdir
$(OUT_DIR) ; fi
Of course this is not the whole makefile, other definitions make it too
long to post here all. But I think the variable names are
self-explanatory. Also for the pattern rule I give vpath for the make
to locate all the cpp files, and give the required flag for the
compiler to place the object files to the "obj" directory.
Ok. When I ran make, it compiled all the source files to object files
and places object files under "obj" directory. However, when the
linking started weird things happened.
At first there came and error message from the linker that "cannot open
input file secondfile.obj". It is the linker error 1181 of Microsoft
linker. After this message when I ran make with all the objects exist,
no error came. Moreover, when I ran make after erasing all the object
files except the "firstfile.obj" it still linked. But considering these
undeterminancies, the output file was really small (3KB) and I could
not run the output file, link was not successful although there was no
error.
I guess the reason for the error is the rule that runs the linker
cannot find all the object files that are given as prerequisities to
it. I also give the "obj" directory to vpath of course. To overcome
this, I tried:
$(OUTFILE) : $(OBJ_DIR)$(OBJECTS)
But this time I got an error from GNU make that "No rule to make target
firstfile.obj". I thought that this error was from the pattern rule. As
I read from some of the post offering solution to such a problem I
tried a modification to the pattern rule. But, I also got the same
error when I changed the pattern rule to be:
$(OBJ_DIR)%.obj : %.cpp
Can anyone please offer a solution to this problem?
By the way, I am using Windows port of GNU Make, version 3.80, from
Cygwin.
Thanks...
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