Hello, consider this Makefile I have for a project I'm developing on
Windows:
CXX = g++
CXXFLAGS = -Wall -W -ansi -pedantic -g -O0 -DWIN32_LEAN_AND_MEAN -c
LDFLAGS = -mwindows -lcomctl32 -lole32 -o $(EXEC)
EXEC = sfv_checker.exe
OBJECTS = crc32.o globals.o main_window_procedure.o winmain.o
sfv_checker.res
all: $(OBJECTS)
$(CXX) $^ $(LDFLAGS)
%.o: %.cpp
$(CXX) $(CXXFLAGS) $<
%.res: %.rc
windres $< -O coff -o $@
clean:
rm -f $(OBJECTS) $(EXEC) *~ *.stackdump
As you can deduce, I have .cpp-files named globals, winmain, and
main_window_procedure. I also have code in two headers files that are
included by the main_window_procedure.cpp: base_list_view.hpp and
sfv_list_view.hpp. My problem is that when I do a change in either
header and then perform a make, make doesn't think anything needs to be
recompiled. So I end up doing $ make clean ; make which, of course,
rebuilds everything. How should I teach make to recompile files
dependent on the headers I mentioned above whenever they have been
changed?
Thanks for reading!
/ E
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