"Kiran" <[EMAIL PROTECTED]> wrote:
> I have the following, but it compiles into the source itself.
> %.o:%.c
> $(CC) -c $< -o $@
The above pattern and way to call your compiler will place the object file
in the same directory as the source file. The rule uses "%" as a pattern
and the string replaces % in the target will also replace % in the
prerequisite. Example, if you need to create two files, foo.o and
bar/foobar.o The above will expand to two rules:
foo.o: foo.c
$(CC) -c $< -o $@
bar/foobar.o: bar/foobar.c
$(CC) -c $< -o $@
At http://www.gnu.org/software/make/manual/make.html you have probably
already read that $< expands to the name of the first prerequisite and
that $@ expands to the target. So the rule above finally expands to
something like:
bar/foobar.o: bar/foobar.c
$(CC) -c bar/foobar.c -o bar/foobar.o
What you want to do is to use a rule like this:
path/obj_files/%.o: path/src_files/%.c
$(CC) -c $< -o $@
regards Henrik
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