Hello list... I'm new to writing makefiles!
I want to do the following: `make ARGS= "exec_file src_1 src_2 etc"' I realize that $(ARGS) will contain _all_ the arguments. I need to come up with a way to split out each argument to get to: EXEC-FILE = exec_file SRCS = src_1 src_2 src_3 I'm trying to create a "generic" makefile for a non-C compiler. Is this possible? TIA... -- Duke
