On Sunday 04 November 2007, Werner Hoch wrote: > Yes but knowing the syntax would still be nice.
There is no proper document defining a "spice" format. It depends on which variant. All of them are a little different, just different extensions and implementations where there is no real spec. That is one of the advantages of Verilog and VHDL. There is a document describing the syntax. To find out whether something like this is a bug or feature, just compare to the official document. One problem with standards is that they define only what is correct. They usually say nothing about what should happen when the data is incorrect. Often, it works anyway, for a while. _______________________________________________ Help-gnucap mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-gnucap
