Hi, I'm just experimenting with gnucap so all my circuits are very simple. See the following example with a single CMOS inverter. Transistor models were previously posted to gnucap-dev mailing lis and can be downloaded from: http://www.dattalo.com/spice/TSMC_025u_Mosis.txt
=========== * test .include TSMC_025u_Mosis.txt .subckt inv vdd vss out in Mp out in vdd vdd CMOSP l=0.25u w=1.5u Mn out in vss vss CMOSN l=0.25u w=1.0u .ends inv .parameter p_vdd=2.5 vvdd vdd vss 'p_vdd' vvss vss 0 0 vin in vss pwl (0 0, 10n 0, 10.1n 'p_vdd', 20n 'p_vdd', 20.1n 0, 30n 0, 30.1n 'p_vdd') x1 vdd vss n1 in inv .probe tran v(in) v(n1) .dc * this causes a problem .tran 0.01n 40n >out.dat * this works fine but there is ringing on v(n1) waveform .tran 0.1n 40n >out.dat .END =========== -r. On Nov 30, 2007 2:03 AM, Leandro Marsó <[EMAIL PROTECTED]> wrote: > 2007/11/29, a r <[EMAIL PROTECTED]>: > > When using a TSMC 0.25 MOSIS models (level=49) setting the time step > > below 0.1ns like below: > > > > .tran 0.01n 40n > > > > causes following problems. > > > > storage element step control error:Cgs.Mn1.xgate 1e-12 > > using Euler, disabling time step control > > > > With timestep of 0.1ns the simulation runs fine but the numerical > > ringing is very visible. > > > > Any idea? > > > > -r. > > Hello -r, > be carefull with the units in the length and width of the channel, it > is in meter units. If it is not the problem, you could try to isolate > the problem with a small circuit and paste it and send it to the list. > good luck! > Leandro > > > _______________________________________________ > Help-gnucap mailing list > [email protected] > http://lists.gnu.org/mailman/listinfo/help-gnucap > _______________________________________________ Help-gnucap mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-gnucap
