folks:
I have Makefiles spread over multiple sub-directories like given below.
Every time I make *link_all* target (and thus causing all pre-requsities -
lib*_ref_model.so to be re-evaluated,) I would like that the implicit
rule "$objects" in all sub-directories A, B and C are run - if there is a
modification of source files in any of these sub-directories.
What modifications do I need to the $pwd/Makefile?
aditya
--------------------------------------------------
$pwd/Makefile:
CC= g++
# Loader Flags
LDFLAGS=-melf_i386 -lstdc++ -lm
# C flags for compilation
CXXFLAGS= -pipe\
-m32\
-O\
-g\
+error+5 \
-I$(Some_lib)/include \
-I./
REF_SRC_DIR = .
objects := $(patsubst %.cpp,%.o,$(wildcard $(REF_SRC_DIR)/*.cpp))
export
libref_model.so: $(objects)
${CC} -shared $^ -o $@
libA_ref_model.so:
${MAKE} --dir=A libA_ref_model.so
libB_ref_model.so:
${MAKE} --dir=B libB_ref_model.so
libC_ref_model.so:
${MAKE} --dir=C libC_ref_model.so
link_all:libref_model.so libA_ref_model.so libB_ref_model.so
libC_ref_model.so
some_compiler -lref_model -lA_ref_model -lB_ref_model -lC_ref_model -o
some_executable
./some_executable
$pwd/A/Makefile
REF_SRC_DIR = .
objects := $(patsubst %.cpp,%.o,$(wildcard $(REF_SRC_DIR)/*.cpp))
libA_ref_model.so: $(objects)
${CC} -shared $^ -o ../$@
$pwd/B/Makefile
REF_SRC_DIR = .
objects := $(patsubst %.cpp,%.o,$(wildcard $(REF_SRC_DIR)/*.cpp))
libB_ref_model.so: $(objects)
${CC} -shared $^ -o ../$@
$pwd/C/Makefile
REF_SRC_DIR = .
objects := $(patsubst %.cpp,%.o,$(wildcard $(REF_SRC_DIR)/*.cpp))
libC_ref_model.so: $(objects)
${CC} -shared $^ -o ../$@
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