Hi, I was trying out the multi-architecture build scheme described in http://www.paulandlesley.org/gmake/multi-arch.html I encountered a problem. (I am using GNU make 3.79 on a Solaris 2.5.1.) The problem occurs when MAKE is called recursively from the "top-level" Makefile. Looks like instead of $(MAKE), I need to use $(MAKETARGET) -- see below. What is happening? --start of Makefile-- ifeq (,$(filter _%,$(notdir $(CURDIR)))) include target.mk else VPATH = .. CC = gcc all: foo foo: foo.o gcc -o $@ $< try: @echo try invoked $(MAKE) try2 try2: @echo try2 invoked endif --end of Makefile-- and my target.mk follows: --start of target.mk-- .SUFFIXES: OBJDIR := _obj MAKETARGET = $(MAKE) --no-print-directory -C $@ \ -f $(CURDIR)/Makefile SRCDIR=$(CURDIR) \ $(MAKECMDGOALS) .PHONY: $(OBJDIR) $(OBJDIR): +@[ -d $@ ] || mkdir -p $@ +@$(MAKETARGET) Makefile: ; %.mk :: ; % :: $(OBJDIR) ; : .PHONY: clean clean:: rm -rf $(OBJDIR) --end of target.mk-- This is the output: $ gmake try2 try2 invoked : $ gmake try try invoked gmake try2 gmake[2]: *** No rule to make target `try2'. Stop. gmake[1]: *** [try] Error 2 gmake: *** [_obj] Error 2 Is this behaviour expected? Should I be using $(MAKETARGET) instead of $(MAKE) for recursive calls? Regards Sankar -- Sankaranarayanan K. V. | [EMAIL PROTECTED] Motorola India Electronics Ltd | http://www.mot.com/miel _______________________________________________ Help-make mailing list [EMAIL PROTECTED] http://mail.gnu.org/mailman/listinfo/help-make
