I have a problem.
My current makefile structure is
Makefile:
prog: lib
prog lib:
for x in A B ; do $(MAKE) -C $x $@ ; done
A/Makefile:
lib: libA.a
prog: progA
libA.a: libA.a(x.o y.o)
progA: progA.o libA.a ../B/libB.a
B/Makefile:
lib: libB.a
prog: progB
libB.a: libB.a(x.o y.o)
progB: progB.o ../A/libA.a libB.a
Now I want to make it possible to build this with as much paralelism as
possible, how should that be done?
One approach is to use .PHONY subdirectories as targets but that fails
since it is all but impossible to specify the target that is to be built.
Another approach is to use special targets for each combination of
subdirectory and target but that gets unvieldy rather quick when more
target directories are added.
I am out of good ideas.
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