Hi, everybody:
I have a project with several executable targets. The building progress
for all of these targets are nearly same, except there dependent source
codes. In the meanwhile, I may add some other executable targets in
this project. Hence I want to write a unified Makefile so that it
can add some new targets by just adding project name into target list.
So my idea is:
for each target, create a file named as $(target name).list
in this file, I can put the list of source codes.
In Makefile, there is a macro named as "MODULE_LIST", which
contains the list of my targets. I hope that Makefile can
check the source codes for each target automatically.
Following is main part of my Makefile:
========================================================================
MODULE_LIST = proj1 proj2 proj3 ...
all: $(MODULE_LIST)
$(MODULE_LIST):%:
override MODULE_SOURCE = $(sort $(filter-out /%, $(shell cat \
$*.list)))
override MODULE_OBJS = $(MODULE_SOURCE:%.c=%.o)
$(MODULE_LIST):%: $(MODULE_OBJS)
$(MODULE_OBJS): $(MODULE_SOURCE)
$(CC) -c $< -o $@
...
========================================================================
But it doesn't work. Because $(MODULE_OBJS) can only be expanded in the
body of "$(MODULE_LIST):%:" rule.
could you please tell me how to do it?
Thanks in advance.
Sincerely
--
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Lei Yin, Ph.D
Celestry Design Technologies, Inc
1982A Zanker Road, San Jose, CA 95112
Tel: (408)501-2313(O) | Fax: (408)501-2607
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
"I'd change the world but God won't give me the source code" -- Anonymous
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