%% Regarding $$@; you wrote:
mf> It says in the make manual that part of the functionality from $$@
mf> can be gained by means of static pattern rules. Is the following
mf> snippet of a makefile possible to translate into GNU make syntax?
It can be, but not using static pattern rules.
mf> $(PROGS): $($$(@F)_OBJS) $($$(@F)_LIBS)
In order to do something like this, you'll have to use GNU make's
auto-re-exec feature to construct a makefile part and include it.
Maybe:
PROGS=bin/A bin/B
A_OBJS=a.o c.o
B_OBJS=b.o d.o
A_LIBS=lib/libE.a
B_LIBS=lib/libF.a
include progs.mk
progs.mk: Makefile
rm -f $@
for d in $(PROGS); do \
f=`basename $$d`; \
echo "$$d : \$$($${f}_OBJS) \$$($${f}_LIBS) ; \\" >> $@; \
echo ' $$(LINK.c) $$^ -o $$@' >> $@; \
done
Note I simplified your link line by using $^ instead of retyping the
variables.
--
-------------------------------------------------------------------------------
Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at:
http://www.gnu.org http://www.paulandlesley.org/gmake/
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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