%% Anton Deguet <[EMAIL PROTECTED]> writes:
ad> I want to build multiple lists of files based on the same string
ad> substitution using some kind of loop. I tried something with foreach,
ad> that is:
ad> libs = lib1 lib2
ad> lib1_cfiles_prefix = file1 file2 file3
ad> lib2_cfiles_prefix = fichier1 fichier2 fichier3
ad> now I want to build some object lists called lib1_obj, lib2_obj, etc...
ad> which would contain:
ad> lib1_obj = my_bin_dir/file1.o my_bin_dir/file2.o my_bin_dir/file3.o
ad> lib2_obj = my_bin_dir/fichier1.o my_bin_dir/fichier2.o ...
The expansion of functions in general cannot themselves be complete make
command line such as variable settings. And although this kind of works
in some limited conditions, they absolutely cannot expand to multiple
lines and have that work in any way.
This is the major new feature to be added in GNU make 3.80.
ad> Can I force some kind of evaluation to set the variable during the
ad> iteration of the foreach?
No.
ad> Any other solution/suggestion is welcome.
You can create a rule which writes the results of the expansion out to a
file, then include that file in your makefile:
include variable.mk
variable.mk: Makefile
@rm -f $@
@for l in $(libs); do \
echo "$$l"'_obj = $$('"$$l"'_cfiles_prefix:%=my_bin_dir/%.o))' >> $@; \
done
or something like that. For the example you give here it's not really
clear to me that it's worth all this trouble, but maybe your actual code
is more complicated.
--
-------------------------------------------------------------------------------
Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at:
http://www.gnu.org http://www.paulandlesley.org/gmake/
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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