I have two questions regarding target specific variables.
1. I want to use $@ in a dependency of the current target by assigning
it to another variable. This does not appear to work because $@
changes whenever a new target is in operation.
2. I want to override a variable and then test its value in a later
target. This does not appear to work. See examples below.
The documentation states that: '...when you define a target-specific
variable,
that variable value is also in effect for all prerequisites of this
target...'
Our installed version is 3.79 on Solaris, but I have also tried 3.79.1.
Makefile
all: $(TESTS)
TESTS = mytest bist scan
.PHONY: $(TESTS)
$(TESTS): TESTBENCH=$@
$(TESTS): override TESTVAR=TRUE
$(TESTS): COMPILE
@echo "\nLVTESTS Target"
@echo "target $@, dep $<""
@echo "TESTBENCH=$(TESTBENCH)"
@echo "TESTVAR=$(TESTVAR)"
COMPILE:
@echo "\nCOMPILE Target"
@echo "target $@, dep $<"
@echo "TESTBENCH=$(TESTBENCH)"
@echo "TESTVAR=$(TESTVAR)"
ifeq ($(TESTVAR),TRUE)
@echo "TESTVAR is TRUE"
else
@echo "TESTVAR is NOT TRUE!"
endif
$ make -f Makefile.test mytest TESTVAR=FALSE
COMPILE Target
target COMPILE, dep
TESTBENCH=COMPILE <<<<< I want this to be mytest at this point
TESTVAR=TRUE
TESTVAR is NOT TRUE! <<<< should be overridden
LVTESTS Target
target mytest, dep COMPILE
TESTBENCH=mytest
TESTVAR=TRUE
$ make -f Makefile.test mytest
COMPILE Target
target COMPILE, dep
TESTBENCH=COMPILE
TESTVAR=TRUE
TESTVAR is NOT TRUE! <<<< should be overridden
LVTESTS Target
target mytest, dep COMPILE
TESTBENCH=mytest
TESTVAR=TRUE
$ make -f Makefile.test mytest TESTVAR=TRUE
COMPILE Target
target COMPILE, dep
TESTBENCH=COMPILE
TESTVAR=TRUE
TESTVAR is TRUE <<<< yes, but it's taken from the command line
LVTESTS Target
target mytest, dep COMPILE
TESTBENCH=mytest
TESTVAR=TRUE
- Paul Smith
_______________________________________________
Help-make mailing list
[EMAIL PROTECTED]
http://mail.gnu.org/mailman/listinfo/help-make
