Hi,
I have the following problem with 'make'
I am using the recursive make feature.
At the top level there is a makefile which has the following relevant
parts
------------------------------------------------------------------------
-------------------------------
include <filename1>
..
..
..
clean
cd ../subdir1/subdir2 && $(MAKE) clean
------------------------------------------------------------------------
-------------------------------
Now ../subdir1/subdir2 has a Makefile which has the following relevant
parts
------------------------------------------------------------------------
-------------------------------
include <filename>
..
..
if (condition)
VAR1 = $(VAR) xyz // $VAR is defines in the include file
endif
module:
$(CC).....FLAGS.....$(VAR1).....
------------------------------------------------------------------------
-------------------------------
when I execute $(MAKE) from the toplevel makefile, VAR1 is not getting
resolved.
There are few variables defined in the include file 'filename1'
Both the makefiles are including the same include file 'filename1', but
the sub-make file is not able to see these variables when called from
the top level make file.
However, when the sublevel make is run independently, it works fine.
So I gave a export command on the toplevel make file so that all the
variables are exported thru the environment to the sub-make
files(because anyway the same file is included).
Now all of the variables defined in the include file get known to the
sub level make file, but VAR1 is not resolved. Its empty. VAR1 is not
defined in the include file. It is constructed using a variable VAR
which is defined in the include file.
I dunno where things are wrong.
Any help would be appreciated.
Thanks and Rgds,
Satheesh
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