At 11:52 PM 10/18/2002 -0400, Paul D. Smith wrote:
Now I understand much better.Or you could put this into a variable assignment, where it won't be parsed as a possible rule:_x := $(if $(RECURSE), $(shell RECURSE=; $(MAKE) recurse ) ) This is typically how $(shell ...) would be used, otherwise the output of the make command would be considered make syntax which should be parsed, which is probably not what you want.
Yes, the method you suggest above does work but the problem is that output is 'swallowed' by assignment to _x and doesn't appear in the terminal.
I would like to be have $(MAKE) recurse run just like if I had typed 'make recurse' on the command line.
I wanted to do something similar with a 'debug' rule to echo some makefile variables to the terminal; to somehow invoke the rule from the makefile, without it having to be a target.
The problem I am trying to solve is:
* I do not want to specify 'recurse' as a command line goal; I want to build $(MAKECMDGOALS) in each directory in my list:
recurse :
@for dir in $(SUBDIRS); do\
$(MAKE) -C $$dir $(MAKECMDGOALS); \
done
I could add 'recurse' as a command line goal, then remove it from $(MAKECMDGOALS) in the makefile:
GOALS = $(filter-out recurse, $(MAKECMDGOALS) )
recurse :
@for dir in $(SUBDIRS); do\
$(MAKE) -C $$dir $(GOALS); \
done
This seems a bit awkward though.
Can anyone suggest a more straight-forward way to explicitly execute a rule?
Thanks,
Greg Keraunen <[EMAIL PROTECTED]>
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