I don't understand why make is trying to rebuild my Makefile.o, in the
example below.
It seems like my pattern rules must have screwed up the implicit rules or
something.
If I use 'make -r foo.c' I don't have a problem.
I am trying to understand how implicit rules work so that I can:
1. write my own rules which should take precedence over built-in rules and
not break things
2. avoid disabling all built-in implicit rules which may be useful if I
have not pre-emted them in my makefile
[greg@p3 junk]$ make foo.c
rule: %.c target: Makefile.c
cc -c -o Makefile.o Makefile.c
cc: Makefile.c: No such file or directory
cc: No input files
make: *** [Makefile.o] Error 1
# Makefile
.PHONY: force
foo: force
@echo $@
/%.c: force
@echo 'rule: /%.c' "target: $@"
%.c: force
@echo 'rule: %.c' "target: $@"
# eof
- Greg Keraunen
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