Hi All,
I am just starting to get the hang of makefiles until I came across this
small problem. Below is a small makefile to show the problem.
.PHONY: debug all
OBJECTS := fred.txt
CDE := debug.txt
debug : OBJECTS = $(OBJECTS) $(CDE)
debug : all
all : $(OBJECTS)
@echo $(OBJECTS) "executing target=all"
fred.txt :
@echo $(OBJECTS) "executing target=fred.txt"
debug.txt :
@echo $(OBJECTS) "executing target=debug.txt"
If I execute "make all", I get
fred.txt executing target=fred.txt
fred.txt executing target=all
If I execute "make debug", I get
fred.txt debug.txt executing target=fred.txt
fred.txt debug.txt executing target=all
My question is shouldn't the "debug" target cause it to include debug.txt as
a dependency as well as fred.txt? The above small test does not seem to back
this up.
Any assistance is welcome.
thanks,
Tehn Yit Chin
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