Hi,firstly,
I have a question about writing Makefile. Could any one help me.
Question: As I do my project using gnu make, I have sub_directories and I would like the files/directories under these subdirectories been compiled.
Therefore I create a makefile as follows:
SUB_DIRS = src vlan ip lib # (I have 4 subdirs-- src, vlan, ip, and lib)
all: for subdir in $(SUBDIRS) ; do \
make -C $subdir; \
done;
So that I can "make -C" to each sub-directory and get them compiled. However, Make utility seems can not support this kind of for-loop.
Are there any way in make utility to get this for-loop done?
If you need to access a shell variable, you'll need to pass a `$' to the shell.
To do so, you'll need to escape it with an additional `$' like so:
make -C $$subdir;
Furthermore, (as discussed in another mail on this list just today), you will loose any exit value from the sub-make, if you wish to trap the errors you should at least do this:
make -C $$subdir || exit -1;
read:
http://mail.gnu.org/archive/html/help-make/2003-09/msg00028.html
for something a little more scalable.Cheers,
-Tristan
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