################################################################
define make-variables
FOO = foo
BAR = bar
endef
$(make-variables)
echo:
# $(FOO)
# $(BAR)
################################################################
When executed make reports
Makefile:5: *** missing separator. Stop.
Why?
I know I can resolve the issue by wrapping the variable expansion in
$(eval ), but that isn't my question. I just want to know why the
expansion generates the error. The define construct explicitly
preserves newlines in the expansion so I would think the parser would
simply see two assignments separated by a newline. Evidently not.
I've just managed to build make from CVS with some trouble (if you
want, I can report my problems more properly), so I'll dive in with
gdb right now, but maybe someone on the list is willing to lend me
their insight.
Thanks,
--
Robert
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