Consider this Makefile :
toto: toto.o
toto: CFLAGS=-g
%.o: %.c
gcc -o $@ -c $< $(CFLAGS)
%: %.o
gcc -o $@ $<
If I run 'make toto toto.o', I get :
gcc -o toto.o -c toto.c -g
gcc -o toto toto.o
but 'make toto.o toto' gives :
gcc -o toto.o -c toto.c
gcc -o toto toto.o
So, it looks like variable definitions in static patterns can "propagate"
to dependencies. While it can be useful, it is also quite confusing.
Is it a bug, that may be fixed one day, or a feature that we can rely on ?
-- Benoit
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