hello,
consider the following Makefile, working under linux, make 3.80
------------------------------
test2: OBJECTS=$(shell ls a.o)
test2: $(shell ls a.o)
test2: $(OBJECTS)
echo $(OBJECTS)
touch test2
-------------------------------
the following commands
# > touch a.o
# > make
# > make
# > touch a.o
# > make
the first and third time make is issued the echo happens, well that's the
intended behaviour. If you remove the second test2 target, only the first
make will issue the echo, why?
My real shell command is quite long, and i don't want to write it twice.
best regards
Andre Maute
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