On Wed, May 05, 2004 at 10:49:00AM -0400, Lars Kellogg-Stedman wrote:
# > Because space is a hard delimiter in the code.
# >
# > A workaround I use is to define a variable like so (But this does not always
# > work)
# >
# > spc=$(x) $(x)
#
# Thanks for the note...but I think you misread my posting. I already
# pointed out that this:
#
# filename=two\ words
#
# works just fine.
No, it doesn't, at least not for all makes, e.g. BSD make:
$ cat Makefile
filename=two\ words
$(filename):
@echo $@
$ make 'two\'
two\
$ make words
words
$ make 'two words'
make: don't know how to make two words. Stop
Paul, I wonder if BSD make or GNU make behaves according to SUSv3.
Shouldn't all macros be expanded while reading a target line?
Regards,
Jens
--
Jens Schweikhardt http://www.schweikhardt.net/
SIGSIG -- signature too long (core dumped)
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